CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices.
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- Electrical Engineering
- line edge roughness
- random dopant
- threshold variation
- Variables (Mathematics)
- Metal oxide semiconductors, Complementary--Mathematical models.
- Metal oxide semiconductors, Complementary
- Integrated circuits--Design and construction--Mathematical models.
- Integrated circuits
- Nanotechnology--Mathematical models.
- Partial requirement for: Ph.D., Arizona State University, 2011Note typethesis
- Includes bibliographical references (p. 97-104)Note typebibliography
- Field of study: Electrical engineering