Matching Items (16)

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In situ electromigration and reliability of Pb-free solders at extremely small length scales

Description

Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable

Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable the increase in density of integrated circuits without necessarily shrinking the dimensions of the device. Under such constraints, the solder volume necessary to join the various layers of the package is also extremely small. At smaller length scales, the local cooling rates are higher, so the microstructures are much finer than that obtained in larger joints (BGA, C4). The fraction of intermetallic compounds (IMCs) present in solder joints in these volumes will be larger. The Cu6Sn5 precipitate size and spacing, and Sn grain structure and crystallography will be different at very small volumes. These factors will most certainly affect the performance of the solder. Examining the mechanical behavior and reliability of Pb-free solders is difficult, primarily because a methodology to characterize the microstructure and the mechanics of deformation at these extremely small length scales has yet to be developed.

In this study, Sn grain orientation and Cu6Sn5 IMC fraction, size, and morphology are characterized in 3D, in pure Sn based solder joints. The obtained results show differences in morphology of Sn grains and IMC precipitates as a function of location within the solder joint indicating influence of local cooling rate differences. Ex situ and in situ electromigration tests done on 250 um and 500 um pure Sn solder joints elucidate the evolution of microstructure, specifically Sn grain growth, IMC segregation and surface degradation. This research implements 3D quantification of microstructural features over micro and nano-scales, thereby enabling a multi-scale / multi-characterization approach.

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Agent

Created

Date Created
  • 2016

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A structured design methodology for high performance VLSI arrays

Description

The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market

The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.

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Agent

Created

Date Created
  • 2012

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Design of a modified Cherry-Hooper transimpedance amplifier with DC offset cancellation

Description

Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to

Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for each receiver. High speed digital communication require high throughput with enough sensitivity to keep the bit error rate low. Instrumentation receivers have a lower bandwidth, but higher gain and sensitivity requirements. In this thesis an optical receiver for use in instrumentation in presented. It is an entirely monolithic design with the photodiodes on the same substrate as the CMOS circuitry. This allows for it to be built into a focal-plane array, but it places some restriction on the area. It is also designed for in-situ testing and must be able to cancel any low frequency noise caused by ambient light. The area restrictions prohibit the use of a DC blocking capacitor to reject the low frequency noise. In place a servo loop was wrapped around the system to reject any DC offset. A modified Cherry-Hooper architecture was used for the transimpedance amplifier. This provides the flexibility to create an amplifier with high gain and wide bandwidth that is independent of the input capacitance. The downside is the increased complexity of the design makes stability paramount to the design. Another drawback is the high noise associated with low input impedance that decouples the input capacitance from the bandwidth. This problem is compounded by the servo loop feed which leaves the output noise of some amplifiers directly referred to the input. An in depth analysis of each circuit block's noise contribution is presented.

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Agent

Created

Date Created
  • 2011

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System identification of linear and switching regulators using switched capacitor correlator

Description

Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits

Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management circuits is the measurement of their frequency response for stability assessment. The standard techniques used in production test environment require expensive measurement equipment (Network Analyzer) and time. These two issues of component variations and frequency response measurement can be addressed if the frequency response of the power converter is used as measure of component (capacitor and inductor) variations. So, a single solution of frequency response measurement solves both the issues. This work examines system identification (frequency response measurement) of power management circuits based on cross correlation technique and proposes the use of switched capacitor correlator for this purpose. A switched capacitor correlator has been designed and used in the system identification of Linear and Switching regulators. The obtained results are compared with the standard frequency response measurement methods of power converters.

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Agent

Created

Date Created
  • 2015

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CMOS integrated power amplifiers for RF reconfigurable and digital transmitters

Description

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:

1) A transformer-based power combiner architecture for out-phasing transmitters

2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)

3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters

This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.

The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.

Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.

Contributors

Agent

Created

Date Created
  • 2019

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Power management IC for single solar cell

Description

A single solar cell provides close to 0.5 V output at its maximum power point, which is very

low for any electronic circuit to operate. To get rid of this problem,

A single solar cell provides close to 0.5 V output at its maximum power point, which is very

low for any electronic circuit to operate. To get rid of this problem, traditionally multiple

solar cells are connected in series to get higher voltage. The disadvantage of this approach

is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can

result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)

at single solar cell level is the most efficient way to extract power from solar cell.

Power Management IC (MPIC) used to extract power from single solar cell, needs to

start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area

overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an

auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.

The auxiliary supply powers up a MPPT converter followed by a regulated converter. At

the start up both the converters operate at 100 kHz clock with 80% duty cycle and system

output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up

circuit is turned off and the supply voltage for both the converters is derived from the system

output itself. In steady-state condition the system output is regulated to 3.0 V.

A fully integrated analog MPPT technique is proposed to extract maximum power from

the solar cell. This technique does not require Analog to Digital Converter (ADC) and

Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed

MPPT techniques includes a switch capacitor based power sensor which senses current of

boost converter without using any sense resistor. A complete system is designed which

starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.

Contributors

Agent

Created

Date Created
  • 2015

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Wide input common-mode range fully integrated low-dropout voltage regulators

Description

The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management,

The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.

The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.

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Agent

Created

Date Created
  • 2016

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Automated place and route methodologies for multi-project test chips

Description

This work describes the development of automated flows to generate pad rings, mixed signal power grids, and mega cells in a multi-project test chip. There were three major design flows

This work describes the development of automated flows to generate pad rings, mixed signal power grids, and mega cells in a multi-project test chip. There were three major design flows that were created to create the test chip. The first was the pad ring which was used as the staring block for creating the test chip. This flow put all of the signals for the chip in the order that was wanted along the outside of the die along with creation of the power ring that is used to supply the chip with a robust power source.

The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.

Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.

Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.

Contributors

Agent

Created

Date Created
  • 2015

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New model for simulating impact of negative bias temperature instability (NBTI) in CMOS Circuits

Description

Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and

Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.

The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.

Contributors

Agent

Created

Date Created
  • 2014

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On-chip transformer design and modeling for fully integrated isolated DC/DC converters

Description

Isolated DC/DC converters are used to provide electrical isolation between two supply domain systems. A fully integrated isolated DC/DC converter having no board-level components and fabricated using standard integrated circuits

Isolated DC/DC converters are used to provide electrical isolation between two supply domain systems. A fully integrated isolated DC/DC converter having no board-level components and fabricated using standard integrated circuits (IC) process is highly desirable in order to increase the system reliability and reduce costs. The isolation between the low-voltage side and high-voltage side of the converter is realized by a transformer that transfers energy while blocking the DC loop. The resonant mode power oscillator is used to enable high efficiency power transfer. The on-chip transformer is expected to have high coil inductance, high quality factors and high coupling coefficient to reduce the loss in the oscillation. The performance of a transformer is highly dependent on the vertical structure, horizontal geometry and other indispensable structures that make it compatible with the IC process such as metal fills and patterned ground shield (PGS). With the help of three-dimensional (3-D) electro-magnetic (EM) simulation software, the 3-D transformer model is simulated and the simulation result is got with high accuracy.

In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.

Contributors

Agent

Created

Date Created
  • 2014