Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation.
Download count: 0
- Partial requirement for: Ph.D., Arizona State University, 2014Note typethesis
- Includes bibliographical references (p. 136-141)Note typebibliography
- Field of study: Electrical engineering