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Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation.

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    Date Created
    2012
    Resource Type
  • Text
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    • Partial requirement for: Ph.D., Arizona State University, 2012
      Note type
      thesis
    • Includes bibliographical references (p. 98-107)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Gajanan Dessai

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