Over decades, scientists have been scaling devices to increasingly smaller feature sizes for ever better performance of complementary metal-oxide semiconductor (CMOS) technology to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks.
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- Partial requirement for: M.S.Tech, Arizona State University, 2016Note typethesis
- Includes bibliographical references (page 35)Note typebibliography
- Field of study: Electrical engineering