Matching Items (2)
Description
Public-Private Partnerships (P3) in North America have become a trend in the past two decades and are gaining attention in the transportation industry with some large scale projects being delivered by this approach. This is due to the need for alternative funding sources for public projects and for improved efficiency of these projects in order to save time and money. Several research studies have been done, including mature markets in Europe and Australia, on the cost and schedule performance of transportation projects but no similar study has been conducted in North America. This study focuses on cost and schedule performance of twelve P3 transportation projects during their construction phase, costing over $100 million each, consisting of roads and bridges only with no signature tunnels. The P3 approach applied in this study is the Design-Build-Finance-Operate-Maintain (DBFOM) model and the results obtained are compared with similar research studies on North American Design-Build (DB) and Design-Bid-Build (DBB) projects. The schedule performance for P3 projects in this study was found to be -0.23 percent versus estimated as compared to the 4.34 percent for the DBB projects and 11.04 percent for the DB projects in the Shrestha study, indicating P3 projects are completed in less time than other methods. The cost performance in this study was 0.81 percent for the P3 projects while in the Shrestha study the average cost increase for the four DB projects was found to be 1.49 percent while for the DBB projects it was 12.71 percent, again indicating P3 projects reduce cost compared to other delivery approaches. The limited number of projects available for this study does not allow us to draw an explicit conclusion on the performance of P3s in North America but paves the way for future studies to explore more data as it becomes available. However, the results in this study show that P3 projects have good cost and schedule adherence to the contract requirements. This study gives us an initial comparison of P3 performance with the more traditional approach and shows us the empirical benefits and limitations of the P3 approach in the highway construction industry.
ContributorsBansal, Ankita (Author) / Chasey, Allan (Thesis advisor) / Gibson, Edd (Committee member) / Pendyala, Ram (Committee member) / Arizona State University (Publisher)
Created2012
Description
Over decades, scientists have been scaling devices to increasingly smaller feature sizes for ever better performance of complementary metal-oxide semiconductor (CMOS) technology to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks. Aging due to bias-temperature-instability (BTI) and Hot carrier injection (HCI) is the dominant cause of functional failure in large scale logic circuits. The aging phenomena, on top of process variations, translate into complexity and reduced design margin for circuits. Such issues call for “Design for Reliability”. In order to increase the overall design efficiency, it is important to (i) study the impact of aging on circuit level along with the transistor level understanding (ii) calibrate the theoretical findings with measurement data (iii) implementing tools that analyze the impact of BTI and HCI reliability on circuit timing into VLSI design process at each stage. In this work, post silicon measurements of a 28nm HK-MG technology are done to study the effect of aging on Frequency Degradation of digital circuits. A novel voltage controlled ring oscillator (VCO) structure, developed by NIMO research group is used to determine the effect of aging mechanisms like NBTI, PBTI and SILC on circuit parameters. Accelerated aging mechanism is proposed to avoid the time consuming measurement process and extrapolation of data to the end of life thus instead of predicting the circuit behavior, one can measure it, within a short period of time. Finally, to bridge the gap between device level models and circuit level aging analysis, a System Level Reliability Analysis Flow (SyRA) developed by NIMO group, is implemented for a TSMC 65nm industrial level design to achieve one-step reliability prediction for digital design.
ContributorsBansal, Ankita (Author) / Cao, Yu (Thesis advisor) / Seo, Jae sun (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2016