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Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and

Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.

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    Date Created
    • 2014
    Resource Type
  • Text
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    Note
    • Partial requirement for: M.S., Arizona State University, 2014
      Note type
      thesis
    • Includes bibliographical references (p. 58-62)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Sudheer Padala

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