Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level.
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- Partial requirement for: M.S., Arizona State University, 2014Note typethesis
- Includes bibliographical references (p. 58-62)Note typebibliography
- Field of study: Electrical engineering