We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures.
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- Partial requirement for: Ph.D., Arizona State University, 2014Note typethesis
- Includes bibliographical references (p. 83-86)Note typebibliography
- Field of study: Computer science