In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs.
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- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 22-23)Note typebibliography
- Field of study: Electrical engineering