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In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.

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    Date Created
    • 2013
    Resource Type
  • Text
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    Note
    • Partial requirement for: M.S., Arizona State University, 2013
      Note type
      thesis
    • Includes bibliographical references (p. 22-23)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Kibeom Kim

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