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  4. Digital calibration and prediction of effective number of bits for pipeline ADC
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Digital calibration and prediction of effective number of bits for pipeline ADC

Full metadata

Description

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.

Date Created
2013
Contributors
  • Kim, Kibeom (Author)
  • Ozev, Sule (Thesis advisor)
  • Kitchen, Jennifer (Committee member)
  • Barnaby, Hugh (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Electrical Engineering
  • adaptive prediction
  • ADC
  • Calibration
  • Pipelined ADCs--Calibration.
  • Pipelined ADCs
Resource Type
Text
Genre
Masters Thesis
Academic theses
Extent
vii, 23 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Reuse Permissions
All Rights Reserved
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.21026
Statement of Responsibility
by Kibeom Kim
Description Source
Viewed on May 5, 2014
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2013
Note type
thesis
Includes bibliographical references (p. 22-23)
Note type
bibliography
Field of study: Electrical engineering
System Created
  • 2014-01-31 11:38:18
System Modified
  • 2021-08-30 01:36:24
  •     
  • 1 year 5 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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