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  4. Programmable analog device array (PANDA): transistor-level analog emulation
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Programmable analog device array (PANDA): transistor-level analog emulation

Full metadata

Title
Programmable analog device array (PANDA): transistor-level analog emulation
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
Date Created
2013
Contributors
  • Suh, Jounghyuk (Author)
  • Bakkaloglu, Bertan (Thesis advisor)
  • Cao, Yu (Committee member)
  • Ozev, Sule (Committee member)
  • Kozicki, Michael (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Electrical Engineering
  • Analog integrated circuits
  • Semiconductor switches
  • Emulators (Computer programs)
  • Programmable logic devices
Resource Type
Text
Genre
Doctoral Dissertation
Academic theses
Extent
xii, 68 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Reuse Permissions
All Rights Reserved
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.21008
Embargo Release Date
Mon, 11/30/2015 - 20:06
Statement of Responsibility
by Jounghyuk Suh
Description Source
Viewed on May 1, 2014
Level of coding
full
System Created
  • 2014-01-31 11:37:53
System Modified
  • 2021-08-30 01:36:31
  •     
  • 2 years 3 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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