Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming.
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- Partial requirement for: M.S., Arizona State University, 2011Note typethesis
- Includes bibliographical references (p. 60-62)Note typebibliography
- Field of study: Electrical engineering