Modern Complementary-Metal-Oxide-Semiconductor (CMOS) technologies are facing critical challenges: scaling channel lengths below ~10 nm is hindered by significant transport degradation as bulk semiconductors (i.e., silicon) are thinned down, energy consumption is affected by short-channel effects and off-state leakage, and conventional von Neumann computing architectures face serious bottlenecks affecting performance and efficiency (energy consumption and throughput). Neuromorhic and/or in-memory computing architectures using resistive random-access memory (RRAM) crossbar arrays are promising candidates to mitigate these bottlenecks and to circumvent CMOS scaling challenges. Recently, emerging two dimensional materials (2DMs) are investigated towards ultra-scaled CMOS devices, as well as towards non-volatile memory and neuromorphic devices with potential improvements in scalability, power consumption, switching speed, and compatibility with CMOS integration.The first part of this dissertation presents contributions towards high-yield 2DMs field- effect-transistors (FETs) fabrication using wafer-scale chemical vapor deposition (CVD) monolayer MoS2. This work provides valuable insight about metal contact processing, including extraction of Schottky barrier heights and Fermi-level pinning effects, for next- generation integrated electronic systems based on CVD-grown 2DMs. The second part introduces wafer-scale fabrication of memristor arrays with CVD- grown hexagonal boron nitride (h-BN) as the active switching layer. This work establishes the multi-state analog pulse programmability and presents the first experimental demonstration of dot-product computation and implementation of multi-variable stochastic linear regression on h-BN memristor hardware. This work extends beyond previous demonstrations of non-volatile resistive switching (NVRS) behavior in isolated h-BN memristors and paves the way for more sophisticated demonstrations of machine learning applications based on 2DMs. Finally, combining the benefits of CVD-grown 2DMs and graphene edge contacts, vertical h-BN memristors with ultra-small active areas are introduced through this research. These devices achieve low operating currents (high resistance), large RHRS/RLRS ratio, and enable three-dimensional (3D) integration (vertical stacking) for ultimate RRAM scalability. Moreover, they facilitate studying fundamental NVRS mechanisms of single conductive nano-filaments (CNFs) which was previously unattainable in planar devices. This way, single quantum step in conductance was experimentally observed, consistent with theorized atomically-constrained CNFs behavior associated with potential improvements in stability of NVRS operation. This is supported by measured improvements in retention of quantized conductance compared to other non-2DMs filamentary-based memristors.

In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation. In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.

The research of alternative materials and new device architectures to exceed the limits of conventional silicon-based devices has been sparked by the persistent pursuit of semiconductor technology scaling. The development of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), well-known member of the transition metal dichalcogenide (TMD) family, has made great strides towards ultrascaled two-dimensional (2D) field-effect-transistors (FETs). The scaling issues facing silicon-based complementary metal-oxide-semiconductor (CMOS) technologies can be solved by 2D FETs, which show extraordinary potential.This dissertation provides a comprehensive experimental analysis relating to improvements in p-type metal-oxide-semiconductor (PMOS) FETs with few-layer WSe2 and high-κ metal gate (HKMG) stacks. Compared to this works improved methods, standard metallization (more damaging to underlying channel) results in significant Fermi-level pinning, although Schottky barrier heights remain small (< 100 meV) when using high work function metals. Temperature-dependent analysis reveals a dominant contribution to contact resistance from the damaged channel access region. Thus, through less damaging metallization methods combined with strongly scaled HKMG stacks significant improvements were achieved in contact resistance and PMOS FET overall performance. A clean contact/channel interface was achieved through high-vacuum evaporation and temperature-controlled stepped deposition. Theoretical analysis using a Landauer transport adapted to WSe2 Schottky barrier FETs (SB-FETs) elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance towards the ultimate CMOS scaling limit. Next, this dissertation discusses how device electrical characteristics are affected by scaling of equivalent oxide thickness (EOT) and by adopting double-gate FET architectures, as well as how this might support CMOS scaling. An improved gate control over the channel is made possible by scaling EOT, improving on-off current ratios, carrier mobility, and subthreshold swing. This study also elucidates the impact of EOT scaling on FET gate hysteresis attributed to charge-trapping effects in high-κ-dielectrics prepared by atomic layer deposition (ALD). These developments in 2D FETs offer a compelling alternative to conventional silicon-based devices and a path for continued transistor scaling. This research contributes to ongoing efforts in 2D materials for future semiconductor technologies. Finally, this work introduces devices based on emerging Janus TMDs and bismuth oxyselenide (Bi2O2Se) layered semiconductors.

Machine learning advancements have led to increasingly complex algorithms, resulting in significant energy consumption due to heightened memory-transfer requirements and inefficient vector matrix multiplication (VMM). To address this issue, many have proposed ReRAM analog in-memory computing (AIMC) as a solution. AIMC enhances the time-energy efficiency of VMM operations beyond conventional VMM digital hardware, such as a tensor processing unit (TPU), while substantially reducing memory-transfer demands through in-memory computing. As AIMC gains prominence as a solution, it becomes crucial to optimize ReRAM and analog crossbar architecture characteristics. This thesis introduces an application-specific integrated circuit (ASIC) tailored forcharacterizing ReRAM within a crossbar array architecture and discusses the interfacing techniques employed. It discusses ReRAM forming and programming techniques and showcases chip’s ability to utilize the write-verify programming method to write image pixels on a conductance heat map. Additionally, this thesis assesses the ASIC’s capability to characterize different aspects of ReRAM, including drift and noise characteristics. The research employs the chip to extract ReRAM data and models it within a crossbar array simulator, enabling its application in the classification of the CIFAR-10 dataset.

Resistive random-access memory (RRAM) or memristor, is an emerging technology used in neuromorphic computing to exceed the traditional von Neumann obstacle by merging the processing and memory units. Two-dimensional (2D) materials with non-volatile switching behavior can be used as the switching layer of RRAMs, exhibiting superior behavior compared to conventional oxide-based RRAMs. The use of 2D materials allows scaling the resistive switching layer thickness to sub-nanometer dimensions enabling devices to operate with low switching voltages and high programming speeds, offering large improvements in efficiency and performance as well as ultra-dense integration. This dissertation presents an extensive study of linear and logistic regression algorithms implemented with 1-transistor-1-resistor (1T1R) memristor crossbars arrays. For this task, a simulation platform is used that wraps circuit-level simulations of 1T1R crossbars and physics-based model of RRAM to elucidate the impact of device variability on algorithm accuracy, convergence rate, and precision. Moreover, a smart pulsing strategy is proposed for the practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Next, this dissertation reports on the hardware implementation of analog dot-product operation on arrays of 2D hexagonal boron nitride (h-BN) memristors. This extends beyond previous work that studied isolated device characteristics towards the application of analog neural network accelerators based on 2D memristor arrays. The wafer-level fabrication of the memristor arrays is enabled by large-area transfer of CVD-grown few-layer h-BN films. The dot-product operation shows excellent linearity and repeatability, with low read energy consumption, with minimal error and deviation over various measurement cycles. Moreover, the successful implementation of a stochastic linear and logistic regression algorithm in 2D h-BN memristor hardware is presented for the classification of noisy images. Additionally, the electrical performance of novel 2D h-BN memristor for SNN applications is extensively investigated. Then, using the experimental behavior of the h-BN memristor as the artificial synapse, an unsupervised spiking neural network (SNN) is simulated for the image classification task. A novel and simple Spike-Timing-Dependent-Plasticity (STDP)-based dropout technique is presented to enhance the recognition task of the h-BN memristor-based SNN.

The Deep Neural Network (DNN) is one type of a neuromorphic computing approach that has gained substantial interest today. To achieve continuous improvement in accuracy, the depth, and the size of the deep neural network needs to significantly increase. As the scale of the neural network increases, it poses a severe challenge to its hardware implementation with conventional Computer Processing Unit (CPU) and Graphic Processing Unit (GPU) from the perspective of power, computation, and memory. To address this challenge, domain specific specialized digital neural network accelerators based on Field Programmable Gate Array (FPGAs) and Application Specific Integrated Circuits (ASICs) have been developed. However, limitations still exist in terms of on-chip memory capacity, and off-chip memory access. As an alternative, Resistive Random Access Memories (RRAMs), have been proposed to store weights on chip with higher density and enabling fast analog computation with low power consumption. Conductive Bridge Random Access Memories (CBRAMs) is a subset of RRAMs, whose conductance states is defined by the existence and modulation of a conductive metal filament. Ag-Chalcogenide based Conductive Bridge RAM (CBRAM) devices have demonstrated multiple resistive states making them potential candidates for use as analog synapses in neuromorphic hardware. In this work the use of Ag-Ge30Se70 device as an analog synaptic device has been explored. Ag-Ge30Se70 CBRAM crossbar array was fabricated. The fabricated crossbar devices were subjected to different pulsing schemes and conductance linearity response was analyzed. An improved linear response of the devices from a non-linearity factor of 6.65 to 1 for potentiation and -2.25 to -0.95 for depression with non-identical pulse application is observed. The effect of improved linearity was quantified by simulating the devices in an artificial neural network. Simulations for area, latency, and power consumption of the CBRAM device in a neural accelerator was conducted. Further, the changes caused by Total Ionizing Dose (TID) in the conductance of the analog response of Ag-Ge30Se70 Conductive Bridge Random Access Memory (CBRAM)-based synapses are studied. The effect of irradiation was further analyzed by simulating the devices in an artificial neural network. Material characterization was performed to understand the change in conductance observed due to TID.

This work is aimed at detecting and assessing the performance of colorimetricgold nanoparticle (AuNP) based biosensors, designed to inspect 17-beta-estradiol (E2), SARS-Cov-2 (RBD), and Ebola virus secreted glycoprotein (sGP) with samples at different concentration ranges. The biosensors are able to provide a colorimetric readout, that enables the detection signal to be transmitted via a simple glance, which renders these biosensors cheap and rapid therefore enabling for their implementation into point of care (POC) devices for diagnostic testing in harsh /rural environments, where there is a lack of machinery or trained staff to carry out the diagnosis experiments. Or their implementation into POC devices in medical areas for clinical diagnosis. The intent of this research is to detect the targets of interest such as E2 at a lower limit of detection (LOD), and such as RBD using a novel biosensor design. The verification of the colorimetric results is done via transmission spectra recordings and a compilation of the extinction, where an S-curve relative to the detection concentrations can be seen. This research displays, the fabrication of numerous biosensors and using them in detection experiments to hypothesize the performance of detection using target samples. Additionally, this color change is quantifiable by transmission spectrum recordings to compile the data and calculate the extinction S curve. With the least extinction values pertaining to the highest concentration of detection and the highest extinction values is at the lowest concentration of detection.

Bipolar commercial-off-the-shelf (COTS) circuits are increasingly used in spacemissions due to the low cost per part. In space environments these devices are exposed to ionizing radiation that degrades their performance. Testing to evaluate the performance of these devices is a costly and lengthy process. As such methods that can help predict a COTS part’s performance help alleviate these downsides. A modeling software for predicting total ionizing dose (TID), enhanced low dose rate sensitivity (ELDRS), and hydrogen gas on bipolar parts is introduced and expanded upon. The model is then developed in several key ways that expand it’s features and usability in this field. A physics based methodology of simulating interface traps (NIT) to expand the previously experimental only database is detailed. This new methodology is also compared to experimental data and used to establish a link between hydrogen concentration in the oxide and packaged hydrogen gas. Links are established between Technology Computer Aided Design (TCAD), circuit simulation, and experimental data. These links are then used to establish a better foundation for the model. New methodologies are added to the modeling software so that it is possible to simulate transient based characteristics like slew rate.

The advent of silicon, germanium, narrow-gap III-V materials, and later the wide bandgap (WBG) semiconductors, and their subsequent revolution and enrichment of daily life begs the question: what is the next generation of semiconductor electronics poised to look like? Ultrawide bandgap (UWBG) semiconductors are the class of semiconducting materials that possess an electronic bandgap (EG) greater than that of gallium nitride (GaN), which is 3.4 eV. They currently consist of beta-phase gallium oxide (β-Ga2O3 ; EG = 4.6–4.9 eV), diamond (EG = 5.5 eV), aluminum nitride (AlN; EG =6.2 eV), cubic boron nitride (BN; EG = 6.4 eV), and other materials hitherto undiscovered. Such a strong emphasis is placed on the semiconductor bandgap because so many relevant electronic performance properties scale positively with the bandgap. Where power electronics is concerned, the Baliga's Figure of Merit (BFOM) quantifies how much voltage a device can block in the off state and how high its conductivity is in the on state. The BFOM has a sixth-order dependence on the bandgap. The UWBG class of semiconductors also possess the potential for higher switching efficiencies and power densities and better suitability for deep-UV and RF optoelectronics. Many UWBG materials have very tight atomic lattices and high displacement energies, which makes them suitable for extreme applications such as radiation-harsh environments commonly found in military, industrial, and outer space applications. In addition, the UWBG materials also show promise for applications in quantum information sciences. For all the inherent promise and burgeoning research efforts, key breakthroughs in UWBG research have only occurred as recently as within the last two to three decades, making them extremely immature in comparison with the well-known WBG materials and others before them. In particular, AlN suffers from a lack of wide availability of low-cost, highquality substrates, a stark contrast to β-Ga2O3, which is now readily commercially available. In order to realize more efficient and varied devices on the relatively nascent UWBG materials platform, a deeper understanding of the various devices and physics is necessary. The following thesis focuses on the UWBG materials AlN and β-Ga2O3, overlooking radiation studies, a novel device heterojunction, and electronic defect study.

A Single Event Transient (SET) is a transient voltage pulse induced by an ionizing radiation particle striking a combinational logic node in a circuit. The probability of a storage element capturing the transient pulse depends on the width of the pulse. Measuring the rate of occurrence and the distribution of SET pulse widths is essential to understand the likelihood of soft errors and to develop cost-effective mitigation schemes. Existing research measures the pulse width of SETs in bulk Complementary Metal-Oxide-Semiconductor (CMOS) and Silicon On Insulator (SOI) technologies, but not on Fin Field-Effect Transistors (FinFETs). This thesis focuses on developing a test structure on the FinFET process to generate, propagate, and separate SETs and build a time-to-digital converter to measure the pulse width of SET.



The proposed SET test structure statistically separates SETs generated at NMOS and PMOS based on the difference in restoring current. It consists of N-collection devices to collect events at NMOS and P-collection devices to collect events at PMOS. The events that occur in PMOS of the N-collection device and NMOS of the P-collection device are false events. The logic gates of the collection devices are skewed to perform pulse expansion so that a minimally sustained SET propagates without getting suppressed by the contamination delay. A symmetric tree structure with an S-R latch event detector localizes the location of the SET. The Cartesian coordinates-based pulse injection structure injects external pulses at specific nodes to perform instrumentation and calibrate the measurement. A thermometer-encoded chain (vernier chain) with mismatched delay paths measures the width of the SET.

For low Linear Energy Transfer (LET) tests, the false events are entirely masked and do not propagate since the amount of charge that has to be deposited for successful event propagation is significantly high. In the case of high LET tests, the actual events and false events propagate, but they can be separated based on the SET location and the width of the output event. The vernier chain has a high measurement resolution of ~3.5ps, which aids in separating the events.