Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable the increase in density of integrated circuits without necessarily shrinking the dimensions of the device. Under such constraints, the solder volume necessary to join the various layers of the package is also extremely small. At smaller length scales, the local cooling rates are higher, so the microstructures are much finer than that obtained in larger joints (BGA, C4).
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- Partial requirement for: Ph.D., Arizona State University, 2016Note typethesis
- Includes bibliographical references (pages 100-109)Note typebibliography
- Field of study: Materials science and engineering