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As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but

As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but they become difficult to program. Some existing architectures provide a middle ground by providing some shared memory in the hardware. Specifically, the 48-core Intel Single-chip Cloud Computer (SCC) provides some off-chip (DRAM) shared memory some on-chip (SRAM) shared memory. We call such architectures Hybrid Shared Memory, or HSM, manycore architectures.

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    Date Created
    • 2014
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  • Text
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    • Partial requirement for: M.S., Arizona State University, 2014
      Note type
      thesis
    • Includes bibliographical references (p. 46-48)
      Note type
      bibliography
    • Field of study: Computer science

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    by Tushar Rawat

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