Full metadata
Title
Design of a low power and delay multi-protocol switching system for I/O and network virtualization
Description
Data centers connect a larger number of servers requiring IO and switches with low power and delay. Virtualization of IO and network is crucial for these servers, which run virtual processes for computing, storage, and apps. We propose using the PCI Express (PCIe) protocol and a new PCIe switch fabric for IO and switch virtualization. The switch fabric has little data buffering, allowing up to 512 physical 10 Gb/s PCIe2.0 lanes to be connected via a switch fabric. The switch is scalable with adapters running multiple adaptation protocols, such as Ethernet over PCIe, PCIe over Internet, or FibreChannel over Ethernet. Such adaptation protocols allow integration of IO often required for disjoint datacenter applications such as storage and networking. The novel switch fabric based on space-time carrier sensing facilitates high bandwidth, low power, and low delay multi-protocol switching. To achieve Terabit switching, both time (high transmission speed) and space (multi-stage interconnection network) technologies are required. In this paper, we present the design of an up to 256 lanes Clos-network of multistage crossbar switch fabric for PCIe system. The switch core consists of 48 16x16 crossbar sub-switches. We also propose a new output contention resolution algorithm utilizing an out-of-band protocol of Request-To-Send (RTS), Clear-To-Send (CTS) before sending PCIe packets through the switch fabric. Preliminary power and delay estimates are provided.
Date Created
2013
Contributors
- Luo, Haojun (Author)
- Hui, Joseph (Thesis advisor)
- Song, Hongjiang (Committee member)
- Reisslein, Martin (Committee member)
- Zhang, Yanchao (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
136 p
Language
eng
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.21013
Statement of Responsibility
by Haojun Luo
Description Source
Viewed on May 1, 2014
Level of coding
full
Note
thesis
Partial requirement for: Ph.D., Arizona State University, 2013
Field of study: Electrical engineering
System Created
- 2014-01-31 11:37:59
System Modified
- 2021-08-30 01:36:31
- 3 years 3 months ago
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