Full metadata
Title
Reliable arithmetic circuit design inspired by SNP systems
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
Date Created
2013
Contributors
- An, Pei (Author)
- Cao, Yu (Thesis advisor)
- Barnaby, Hugh (Committee member)
- Chakrabarti, Chaitali (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
viii, 59 p. : ill. (some col.)
Language
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.18806
Statement of Responsibility
by Pei An
Description Source
Viewed on Feb. 24, 2014
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2013
Note type
thesis
Includes bibliographical references (p. 58-59)
Note type
bibliography
Field of study: Electrical engineering
System Created
- 2013-10-08 04:25:25
System Modified
- 2021-08-30 01:38:02
- 2 years 8 months ago
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