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  4. Image processing using approximate data-path units
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Image processing using approximate data-path units

Full metadata

Description

In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24]. First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area. Our implementation of the 2D DCT has comparable PSNR performance with respect to the algorithm presented in [23] with ~35-50% reduction in area. Next, we use the approximate 2x2 multiplier presented in [24] to implement parallel approximate multipliers. We demonstrate that if some of the 2x2 multipliers in the design of the parallel multiplier are accurate, the accuracy of the multiplier improves significantly, especially when two large numbers are multiplied. We choose Gaussian FIR Filter and Fast Fourier Transform (FFT) algorithms to illustrate the efficacy of our proposed approximate multiplier. We show that application of the proposed approximate multiplier improves the PSNR performance of 32x32 FFT implementation by 4.7 dB compared to the implementation using the approximate multiplier described in [24]. We also implement a state-of-the-art image enlargement algorithm, namely Segment Adaptive Gradient Angle (SAGA) [29], in hardware. The algorithm is mapped to pipelined hardware blocks and we synthesized the design using 90 nm technology. We show that a 64x64 image can be processed in 496.48 µs when clocked at 100 MHz. The average PSNR performance of our implementation using accurate parallel adders and multipliers is 31.33 dB and that using approximate parallel adders and multipliers is 30.86 dB, when evaluated against the original image. The PSNR performance of both designs is comparable to the performance of the double precision floating point MATLAB implementation of the algorithm.

Date Created
2013
Contributors
  • Vasudevan, Madhu (Author)
  • Chakrabarti, Chaitali (Thesis advisor)
  • Frakes, David (Committee member)
  • Gupta, Sandeep (Committee member)
  • Arizona State University (Publisher)
Topical Subject
  • Electrical Engineering
  • approximate
  • Image Processing
  • Low Power
  • Image Processing
  • Approximation Theory
  • Multipliers (Mathematical analysis)
Resource Type
Text
Genre
Masters Thesis
Academic theses
Extent
x, 55 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Reuse Permissions
All Rights Reserved
Primary Member of
ASU Electronic Theses and Dissertations
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.20990
Embargo Release Date
Mon, 11/30/2015 - 20:03
Statement of Responsibility
by Madhu Vasudevan
Description Source
Viewed on Apr. 28, 2014
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2013
Note type
thesis
Includes bibliographical references (p. 53-55)
Note type
bibliography
Field of study: Computer science
System Created
  • 2014-01-31 11:37:04
System Modified
  • 2021-08-30 01:36:38
  •     
  • 1 year 6 months ago
Additional Formats
  • OAI Dublin Core
  • MODS XML

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