In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in  and . First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area.
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- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 53-55)Note typebibliography
- Field of study: Computer science