Description
In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24].
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Contributors
- Vasudevan, Madhu (Author)
- Chakrabarti, Chaitali (Thesis advisor)
- Frakes, David (Committee member)
- Gupta, Sandeep (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2013
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Note
- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 53-55)Note typebibliography
- Field of study: Computer science
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Statement of Responsibility
by Madhu Vasudevan