Matching Items (227)
Description新世纪以来中国电影的产业化改革与探索愈发呈现良好的态势，国产院线电影也在实践中努力赢得观众和票房市场。其中类型喜剧电影，最符合商业电影规律、最顺应影视市场需求、最能获得票房收益而备受影视创投机构、制作公司青睐。本论文研究对象聚焦类型喜剧电影，通过“欢声笑语里的财富”现象，探究类型喜剧电影内部本体构成要素与外部客观促成要素的关联；以通过分析自变量与因变量因素对中国电影票房之类型喜剧影响因素进行实证研究，为影视创投和影视制作总结并提供可靠建议。
本论文整体结构包括：第一部分为导论，包括研究背景、目的意义，相关文献综述与文献评述和论文创新性。第二部分聚焦类型喜剧本身，从电影学范畴的电影本体出发，探究“笑”的心理、社会与文化内涵，并分析将“笑”对经济领域的延伸。第三部分以影视投资、票房为依托，从现象和数据中探寻影响类型喜剧电影的因素，为展开中国电影票房之类型喜剧影响因素实证研究做好理论的铺垫。第四与第五部分则基于上述理论进行实证检验，选用2013-2020年电影样本，采用多元线性回归模型研究喜剧类型对票房的吸引力，以及不同种类型喜剧对电影票房的提振效果作用差异。研究发现喜剧电影对电影票房有显著的提振作用；以及研究电影的外部影响因素（续集效应）对电影票房的作用。发现续集电影有更好的票房表现，续集效应的票房提升作用在喜剧电影中表现的更加明显。
本论文研究成果最终将回归到“欢声笑语里的财富”本身；即“类型复合喜剧”对促进电影与金融产业的互动关联、实现更加可持续化发展，以及进而推动经济及文化业的发展。
ContributorsLiu, Yongqian (Author) / Shen, Wei (Thesis advisor) / Zhu, Ning (Thesis advisor) / Dong, Xiaodan (Committee member) / Arizona State University (Publisher)
Created2022
Description人口的老龄化不仅对养老事业提出更高的要求，也对养老服务产业人才的培养提出要求。但是青年学生选择涉老服务专业的意愿却非常低。因此，为了探究职业学院如何增强涉老服务专业吸引力这一问题，本文以学生为主体视角，利用相关理论，对于影响青年学生选择涉老服务专业的因素进行全面的分析，并结合深度访谈和调查法，提出并建构了相关的理论模型。首先，通过深度访谈和焦点小组讨论，结合对现有的文献的分析，本文提出了影响青年学生选择职业院校涉老服务专业的各种因素，主要包括：个人未来风险感知、家庭经济资本、社会信息评价、校企合作水平、专业课程建设水平、学生激励水平、师资队伍建设水平。之后，本文通过调查法，基于社会认同理论构建了本文的研究模型，并通过结构方程模型对所构建的模型进行检查。
本文的研究结果表明：个人未来风险感知对学生专业认同度产生负面影响；家庭经济资本对学生专业认同度产生负面影响；社会信息评价对学生专业认同度产生正面影响；校企合作水平对学生专业认同度产生正面影；专业课程建设水平对学生专业认同度产生正面影响；学生激励水平对学生专业认同度产生正面影响；师资队伍建设水平对学生专业认同度产生正面影响；学生专业认同度对学生专业选择意愿产生正面影响。
基于上述研究结论，本文选取了个人未来风险感知、家庭经济资本、社会信息评价、校企合作水平、专业课程建设水平、学生激励水平、师资队伍建设水平等因素对于广东岭南职业技术学院涉老服务专业的现有吸引力进行了分析和评估，并从这些视角进一步了对如何提升招生吸引力问题进行探讨，为提高涉老服务专业对于青年学生的吸引力，得出了相关管理建议。
ContributorsZhou, Lanqing (Author) / Shen, Wei (Thesis advisor) / Wu, Fei (Thesis advisor) / Pei, Ker-Wei (Committee member) / Arizona State University (Publisher)
Created2021
Description
Edge computing applications have recently gained prominence as the world of internet-of-things becomes increasingly embedded into people's lives. Performing computations at the edge addresses multiple issues, such as memory bandwidth-latency bottlenecks, exposure of sensitive data to external attackers, etc. It is important to protect the data collected and processed by edge devices, and also to prevent unauthorized access to such data. It is also important to ensure that the computing hardware fits well within the tight energy and area budgets for the edge devices which are being progressively scaled-down in size. Firstly, a novel low-power smart security prototype chip that combines multiple entropy sources, such as real-time electrocardiogram (ECG) data, and SRAM-based physical unclonable functions (PUF), for authentication and cryptography applications is proposed. Up to ~12X improvement in the equal error rate compared to a prior ECG-only authentication system is achieved by combining feature vectors obtained from ECG, heart rate variability, and SRAM PUF. The resulting vectors can also be utilized for secure cryptography applications. Secondly, a novel in-memory computing (IMC) hardware noise-aware training algorithms that make DNNs more robust to hardware noise is developed and evaluated. Up to 17% accuracy was recovered in deep neural networks (DNNs) deployed on IMC prototype hardware. The noise-aware training principles are also used to improve the adversarial robustness of DNNs, and successfully defend against both adversarial input and weight attacks. Up to ~10\% improvement in robustness against adversarial input attacks, and up to 33% improvement in robustness against adversarial weight attacks are achieved. Finally, a DNN training algorithm that pursues and optimises both activation and weight sparsity simultaneously is proposed and evaluated to obtain highly compressed DNNs. This lead to up to 4.7x reduction in the total number of flops required to perform complex image recognition tasks. A custom sparse inference accelerator is designed and synthesized to evaluate the benefits of the above flop reduction. A speedup of 4.24x is achieved. In summary, this dissertation contains innovative algorithm and hardware design techniques aided by machine learning, which enhance the security and efficiency of edge computing applications.
ContributorsCherupally, Sai Kiran (Author) / Seo, Jae-Sun (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Cao, Yu (Kevin) (Committee member) / Fan, Deliang (Committee member) / Arizona State University (Publisher)
Created2022
Description
The development of portable electronic systems has been a fundamental factor to the emergence of new applications including ubiquitous smart devices, self-driving vehicles. Power-Management Integrated Circuits (PMICs) which are a key component of such systems must maintain high efficiency and reliability for the final system to be appealing from a size and cost perspective. As technology advances, such portable systems require high output currents at low voltages from their PMICs leading to thermal reliability concerns. The reliability and power integrity of PMICs in such systems also degrades when operated in harsh environments. This dissertation presents solutions to solve two such reliability problems.The first part of this work presents a scalable, daisy-chain solution to parallelize multiple low-dropout linear (LDO) regulators to increase the total output current at low voltages. This printed circuit board (PCB) friendly approach achieves output current sharing without the need for any off-chip active or passive components or matched PCB traces thus reducing the overall system cost. Fully integrated current sensing based on dynamic element matching eliminates the need for any off-chip current sensing components. A current sharing accuracy of 2.613% and 2.789% for output voltages of 3V and 1V respectively and an output current of 2A per LDO are measured for the parallel LDO system implemented in a 0.18μm process. Thermal images demonstrate that the parallel LDO system achieves thermal equilibrium and stable reliable operation.
The remainder of the thesis deals with time-domain switching regulators for high-reliability applications. A time-domain based buck and boost controller with time as the processing variable is developed for use in harsh environments. The controller features adaptive on-time / off-time generation for quasi-constant switching frequency and a time-domain comparator to implement current-mode hysteretic control. A triple redundant bandgap reference is also developed to mitigate the effects of radiation. Measurement results are showcased for a buck and boost converter with a common controller IC implemented in a 0.18μm process and an external power stage. The converter achieves a peak efficiency of 92.22% as a buck for an output current of 5A and an output voltage of 5V. Similarly, the converter achieves an efficiency of 95.97% as a boost for an output current of 1.25A and an output voltage of 30.4V.
ContributorsTalele, Bhushan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Seo, Jae-Sun (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2021
Description
Proton beam therapy has been proven to be effective for cancer treatment. Protons allow for complete energy deposition to occur inside patients, rendering this a superior treatment compared to other types of radiotherapy based on photons or electrons. This same characteristic makes quality assurance critical driving the need for detectors capable of direct beam positioning and fluence measurement. This work showcases a flexible and scalable data acquisition system for a multi-channel and segmented readout parallel plate ionization chamber instrument for proton beam fluence and positioning detection. Utilizing readily available, modern, off-the-shelf hardware components, including an FPGA with an embedded CPU in the same package, a data acquisition system for the detector was designed. The undemanding detector signal bandwidth allows the absence of ASICs and their associated costs and lead times in the system. The data acquisition system is showcased experimentally for a 96-readout channel detector demonstrating sub millisecond beam characteristics and beam reconstruction. The system demonstrated scalability up to 1064-readout channels, the limiting factor being FPGA I/O availability as well as amplification and sampling power consumption.
ContributorsAcuna Briceno, Rafael Andres (Author) / Barnaby, Hugh (Thesis advisor) / Brunhaver, John (Committee member) / Blyth, David (Committee member) / Arizona State University (Publisher)
Created2021
Description
The rapid growth of Internet-of-things (IoT) and artificial intelligence applications have called forth a new computing paradigm--edge computing. Edge computing applications, such as video surveillance, autonomous driving, and augmented reality, are highly computationally intensive and require real-time processing. Current edge systems are typically based on commodity general-purpose hardware such as Central Processing Units (CPUs) and Graphical Processing Units (GPUs) , which are mainly designed for large, non-time-sensitive jobs in the cloud and do not match the needs of the edge workloads. Also, these systems are usually power hungry and are not suitable for resource-constrained edge deployments. Such application-hardware mismatch calls forth a new computing backbone to support the high-bandwidth, low-latency, and energy-efficient requirements. Also, the new system should be able to support a variety of edge applications with different characteristics. This thesis addresses the above challenges by studying the use of Field Programmable Gate Array (FPGA) -based computing systems for accelerating the edge workloads, from three critical angles. First, it investigates the feasibility of FPGAs for edge computing, in comparison to conventional CPUs and GPUs. Second, it studies the acceleration of common algorithmic characteristics, identified as loop patterns, using FPGAs, and develops a benchmark tool for analyzing the performance of these patterns on different accelerators. Third, it designs a new edge computing platform using multiple clustered FPGAs to provide high-bandwidth and low-latency acceleration of convolutional neural networks (CNNs) widely used in edge applications. Finally, it studies the acceleration of the emerging neural networks, randomly-wired neural networks, on the multi-FPGA platform. The experimental results from this work show that the new generation of workloads requires rethinking the current edge-computing architecture. First, through the acceleration of common loops, it demonstrates that FPGAs can outperform GPUs in specific loops types up to 14 times. Second, it shows the linear scalability of multi-FPGA platforms in accelerating neural networks. Third, it demonstrates the superiority of the new scheduler to optimally place randomly-wired neural networks on multi-FPGA platforms with 81.1 times better throughput than the available scheduling mechanisms.
ContributorsBiookaghazadeh, Saman (Author) / Zhao, Ming (Thesis advisor) / Ren, Fengbo (Thesis advisor) / Li, Baoxin (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2021
Description本文在对分子诊断与基因测序相关概念以及文献进行分析和整理的基础上，通过批判分析找到当前研究的空白之处。在此基础上，从理论角度对研发投入、团队背景、应用场景等因素对公司财务绩效的作用机理以及销售模式对研发投入与公司财务绩效关系的调节机理进行分析并提出相关研究假设。利用华大基因、达安基因、凯普生物、金域医学、迪安诊断、艾德生物、透景生命、贝瑞基因等8家分子诊断与基因测序领域上市公司的数据实证了上述研究假设。研究发现：（1）研发投入能够显著促进分子诊断与基因测序公司的财务绩效，但是这种作用效力较小。公司规模和债务水平的提高会降低公司财务绩效，机构投资人持股比例和市场推广费用对公司财务绩效的影响不显著。
（2）创业团队背景的不同并不会导致分子诊断与基因测序公司财务绩效产生差异。
（3）采取直销模式的分子诊断与基因测序公司财务绩效要优于代销和混合模式，后两者公司财务绩效没有显著差异；与代理模式相比，采取直销模式的公司其研发对公司财务绩效的促进作用更加明显，混合模式公司则没有显著差异。
（4）不同产品应用场景的分子诊断与基因测序公司财务绩效，肿瘤的最好，传染病其次，遗传病的排在最后。
ContributorsGuan, Jian (Author) / Shen, Wei (Thesis advisor) / Jiang, Zhan (Thesis advisor) / Sun, Tianshu (Committee member) / Arizona State University (Publisher)
Created2022
Description
Entrepreneurship entails a transition from status quo to a founder/leader of a new organization, and the dominant view in the literature focuses on opportunities in a hypothetical situation, namely an entrepreneurial option. This study shifts the attention from an entrepreneurial option to a current situation and proposes that a perception of costliness in status quo as a driver of entrepreneurial decisions and strategies. Specifically, I propose that a perception of inequality due to the local hierarchy of an organization engenders motivation of disadvantaged employees to become a leader of his/her own entrepreneurial organization. Utilizing hierarchy-based power dynamics and attribution biases, I theorize that i) status gap between a leader and a member and ii) status distinctiveness of a leader in the current organization affect an entrepreneurial decision because of inequality perception. Furthermore, I hypothesize that entrepreneurial organizations driven by such status inequality are more likely to replicate the local structure of the previous employer in terms of status hierarchy to compensate for the perceived disadvantages in the previous employer. The empirical analyses of this study investigate entrepreneurial decisions and entrepreneurial team formation of jazz musicians from jazz discographies between 1950 and 2018, and I found supportive results. This study contributes to the entrepreneurship and inequality literature by bridging two research spaces. It first uncovers the roles of a negative perception of the status quo in entrepreneurship, in addition to the established idea of a positive perception of an alternative option. It also suggests a novel explanation of the long-standing question of inequality reproduction by looking at whether and how inequality spreads via entrepreneurship.
ContributorsJeon, Chunhu (Author) / Shen, Wei (Thesis advisor) / Bundy, Jonathan N (Thesis advisor) / Certo, S. Trevis (Committee member) / Arizona State University (Publisher)
Created2022
Description
This thesis project explores the TID susceptibility of 12nm FinFETs. Along with the basic effects, the mechanisms and patterns of these effects are analyzed and reported.
ContributorsWallace, Trace (Author) / Barnaby, Hugh (Thesis director) / Marinella, Mathew (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / Dean, W.P. Carey School of Business (Contributor)
Created2022-05
Description
Most machine learning algorithms, and specifically neural networks, utilize vector-matrix multiplication (VMM) to process information, but these calculations are CPU intensive and can have long run-times. This issue is fundamentally outlined by the von Neumann bottleneck. Because of this undesirable expense associated with performing VMM via software, the exploration of new ways to perform the same calculations via hardware have grown more popular. When performed with hardware that is specialized to perform these calculations, VMM becomes far more power-efficient and less time consuming. This project expands upon those principles and seeks to validate the use of RRAM in this hardware.
The flexibility of the conductance of RRAM makes these devices a strong contender for hardware-driven VMM calculation for neural network computing. The conductance of these devices is affected by the pulse width of a voltage signal sent across the devices at each node. This pulse is produced on-chip and can be modified by user inputs. The design of this pulse- producing circuit, as well as the simulated and physical functionality of the design, is discussed in this Honors Thesis.
Simulation and physical testing of the pulse-producing design on the ASIC have verified correct operation of the design. This operation is imperative to the future ability of the ASIC to perform accurate VMM.
ContributorsPearson, Katherine (Author) / Barnaby, Hugh (Thesis director) / Wilson, Donald (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor)
Created2022-05