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- All Subjects: engineering
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Karady, George G.
Description
Renewable portfolio standards prescribe for penetration of high amounts of re-newable energy sources (RES) that may change the structure of existing power systems. The load growth and changes in power flow caused by RES integration may result in re-quirements of new available transmission capabilities and upgrades of existing transmis-sion paths. Construction difficulties of new transmission lines can become a problem in certain locations. The increase of transmission line thermal ratings by reconductoring using High Temperature Low Sag (HTLS) conductors is a comparatively new technology introduced to transmission expansion. A special design permits HTLS conductors to operate at high temperatures (e.g., 200oC), thereby allowing passage of higher current. The higher temperature capability increases the steady state and emergency thermal ratings of the transmission line. The main disadvantage of HTLS technology is high cost. The high cost may place special emphasis on a thorough analysis of cost to benefit of HTLS technology im-plementation. Increased transmission losses in HTLS conductors due to higher current may be a disadvantage that can reduce the attractiveness of this method. Studies described in this thesis evaluate the expenditures for transmission line re-conductoring using HTLS and the consequent benefits obtained from the potential decrease in operating cost for thermally limited transmission systems. Studies performed consider the load growth and penetration of distributed renewable energy sources according to the renewable portfolio standards for power systems. An evaluation of payback period is suggested to assess the cost to benefit ratio of HTLS upgrades. The thesis also considers the probabilistic nature of transmission upgrades. The well-known Chebyshev inequality is discussed with an application to transmission up-grades. The Chebyshev inequality is proposed to calculate minimum payback period ob-tained from the upgrades of certain transmission lines. The cost to benefit evaluation of HTLS upgrades is performed using a 225 bus equivalent of the 2012 summer peak Arizona portion of the Western Electricity Coordi-nating Council (WECC).
ContributorsTokombayev, Askhat (Author) / Heydt, Gerald T. (Thesis advisor) / Sankar, Lalitha (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and feature on chip digital mixing. Digital mixing offers many benefits concerning I and Q matching but has one major drawback; the update rate of the DAC must be higher than the intermediate frequency (IF) which is most commonly a factor of 4. This drawback motivates the need for interpolation so that a low update rate can be used for components preceding the DACs. In this thesis the design of an interpolating DAC integrated circuit (IC) to be used in a transmitter application for generating a 100MHz IF is presented. Many of the transistor level implementations are provided. The tradeoffs in the design are analyzed and various options are discussed. This thesis provides a basic foundation for designing an IC of this nature and will give the reader insight into potential areas of further research. At the time of this writing the chip is in fabrication therefore this document does not contain test results.
ContributorsNixon, Cliff (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2013
Description
With the increased penetration of solar PV, it has become considerable for the system planners and operators to recognize the impact of PV plant on the power system stability and reliable operation of grid. This enforced the development of adequate PV system models for grid planning and interconnection studies. Western Electricity Coordinating Council (WECC) Renewable Energy Modeling Task Force has developed generator/converter, electrical controller and plant controller modules to represent positive sequence solar PV plant model for grid interconnection studies. This work performs the validation of these PV plant models against the field measured data. Sheer purpose of this validation effort is to authenticate model accuracy and their capability to represent dynamics of a solar PV plant. Both steady state and dynamic models of PV plant are discussed in this work. An algorithm to fine tune and determine the electrical controller and plant controller module gains is developed. Controller gains as obtained from proposed algorithm is used in PV plant dynamic simulation model. Model is simulated for a capacitor bank switching event and simulated plant response is then compared with field measured data. Validation results demonstrate that, the proposed algorithm is performing well to determine controller gains within the region of interest. Also, it concluded that developed PV plant models are adequate enough to capture PV plant dynamics.
ContributorsSoni, Sachin (Author) / Karady, George G. (Thesis advisor) / Undrill, John (Committee member) / Vittal, Vijay (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Due to increasing integration of renewable resources in the power grid, an efficient high power transmission system is needed in the near future to transfer energy from remote locations to the load centers. Gas Insulated Transmission Line (GIL) is a specialized high power transmission system, designed by Siemens, for applications requiring direct burial or vertical installation of the transmission line. GIL uses SF6 as an insulating medium. Due to unavoidable gas leakages and high global warming potential of SF6, there is a need to replace this insulating gas by some other possible alternative. Insulating foam materials are characterized by excellent dielectric properties as well as their reduced weight. These materials can find their application in GIL as high voltage insulators. Syntactic foam is a polymer based insulating foam. It consists of a large number of microspheres embedded in a polymer matrix.
The work in this thesis deals with the development of the selection proce-dure for an insulating foam for its application in GIL. All the steps in the process are demonstrated considering syntactic foam as an insulator. As the first step of the procedure, a small representative model of the insulating foam is built in COMSOL Multiphysics software with the help of AutoCAD and Excel VBA to analyze electric field distribution for the application of GIL. The effect of the presence of metal particles on the electric field distribution is also observed. The AC voltage withstand test is performed on the insulating foam samples according to the IEEE standards. The effect of the insulating foam on electrical parameters as well as transmission characteristics of the line is analyzed as the last part of the thesis. The results from all the simulations and AC voltage withstand test are ob-served to predict the suitability of the syntactic foam as an insulator in GIL.
The work in this thesis deals with the development of the selection proce-dure for an insulating foam for its application in GIL. All the steps in the process are demonstrated considering syntactic foam as an insulator. As the first step of the procedure, a small representative model of the insulating foam is built in COMSOL Multiphysics software with the help of AutoCAD and Excel VBA to analyze electric field distribution for the application of GIL. The effect of the presence of metal particles on the electric field distribution is also observed. The AC voltage withstand test is performed on the insulating foam samples according to the IEEE standards. The effect of the insulating foam on electrical parameters as well as transmission characteristics of the line is analyzed as the last part of the thesis. The results from all the simulations and AC voltage withstand test are ob-served to predict the suitability of the syntactic foam as an insulator in GIL.
ContributorsPendse, Harshada Ganesh (Author) / Karady, George G. (Thesis advisor) / Holbert, Keith E. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Underground transmission cables in power systems are less likely to experience electrical faults, however, resulting outage times are much greater in the event that a failure does occur. Unlike overhead lines, underground cables are not self-healing from flashover events. The faulted section must be located and repaired before the line can be put back into service. Since this will often require excavation of the underground duct bank, the procedure to repair the faulted section is both costly and time consuming. These added complications are the prime motivators for developing accurate and reliable ratings for underground cable circuits.
This work will review the methods by which power ratings, or ampacity, for underground cables are determined and then evaluate those ratings by making comparison with measured data taken from an underground 69 kV cable, which is part of the Salt River Project (SRP) power subtransmission system. The process of acquiring, installing, and commissioning the temperature monitoring system is covered in detail as well. The collected data are also used to evaluate typical assumptions made when determining underground cable ratings such as cable hot-spot location and ambient temperatures.
Analysis results show that the commonly made assumption that the deepest portion of an underground power cable installation will be the hot-spot location does not always hold true. It is shown that distributed cable temperature measurements can be used to locate the proper line segment to be used for cable ampacity calculations.
This work will review the methods by which power ratings, or ampacity, for underground cables are determined and then evaluate those ratings by making comparison with measured data taken from an underground 69 kV cable, which is part of the Salt River Project (SRP) power subtransmission system. The process of acquiring, installing, and commissioning the temperature monitoring system is covered in detail as well. The collected data are also used to evaluate typical assumptions made when determining underground cable ratings such as cable hot-spot location and ambient temperatures.
Analysis results show that the commonly made assumption that the deepest portion of an underground power cable installation will be the hot-spot location does not always hold true. It is shown that distributed cable temperature measurements can be used to locate the proper line segment to be used for cable ampacity calculations.
ContributorsStowers, Travis (Author) / Tylavsky, Daniel (Thesis advisor) / Karady, George G. (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Shunt capacitors are often added in transmission networks at suitable locations to improve the voltage profile. In this thesis, the transmission system in Arizona is considered as a test bed. Many shunt capacitors already exist in the Arizona transmission system and more are planned to be added. Addition of these shunt capacitors may create resonance conditions in response to harmonic voltages and currents. Such resonance, if it occurs, may create problematic issues in the system. It is main objective of this thesis to identify potential problematic effects that could occur after placing new shunt capacitors at selected buses in the Arizona network. Part of the objective is to create a systematic plan for avoidance of resonance issues.
For this study, a method of capacitance scan is proposed. The bus admittance matrix is used as a model of the networked transmission system. The calculations on the admittance matrix were done using Matlab. The test bed is the actual transmission system in Arizona; however, for proprietary reasons, bus names are masked in the thesis copy in-tended for the public domain. The admittance matrix was obtained from data using the PowerWorld Simulator after equivalencing the 2016 summer peak load (planning case). The full Western Electricity Coordinating Council (WECC) system data were used. The equivalencing procedure retains only the Arizona portion of the WECC.
The capacitor scan results for single capacitor placement and multiple capacitor placement cases are presented. Problematic cases are identified in the form of ‘forbidden response. The harmonic voltage impact of known sources of harmonics, mainly large scale HVDC sources, is also presented.
Specific key results for the study indicated include:
• The forbidden zones obtained as per the IEEE 519 standard indicates the bus 10 to be the most problematic bus.
• The forbidden zones also indicate that switching values for the switched shunt capacitor (if used) at bus 3 should be should be considered carefully to avoid resonance condition from existing.
• The highest sensitivity of 0.0033 per unit for HVDC sources of harmonics was observed at bus 7 when all the HVDC sources were active at the same time.
For this study, a method of capacitance scan is proposed. The bus admittance matrix is used as a model of the networked transmission system. The calculations on the admittance matrix were done using Matlab. The test bed is the actual transmission system in Arizona; however, for proprietary reasons, bus names are masked in the thesis copy in-tended for the public domain. The admittance matrix was obtained from data using the PowerWorld Simulator after equivalencing the 2016 summer peak load (planning case). The full Western Electricity Coordinating Council (WECC) system data were used. The equivalencing procedure retains only the Arizona portion of the WECC.
The capacitor scan results for single capacitor placement and multiple capacitor placement cases are presented. Problematic cases are identified in the form of ‘forbidden response. The harmonic voltage impact of known sources of harmonics, mainly large scale HVDC sources, is also presented.
Specific key results for the study indicated include:
• The forbidden zones obtained as per the IEEE 519 standard indicates the bus 10 to be the most problematic bus.
• The forbidden zones also indicate that switching values for the switched shunt capacitor (if used) at bus 3 should be should be considered carefully to avoid resonance condition from existing.
• The highest sensitivity of 0.0033 per unit for HVDC sources of harmonics was observed at bus 7 when all the HVDC sources were active at the same time.
ContributorsPatil, Hardik U (Author) / Heydt, Gerald T (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2015
Description
Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo-random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
ContributorsBakliwal, Priyanka (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2015
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016