Full metadata
Title
Register file organization for coarse-grained reconfigurable architectures: compiler-microarchitecture perspective
Description
Coarse-Grained Reconfigurable Architectures (CGRA) are a promising fabric for improving the performance and power-efficiency of computing devices. CGRAs are composed of components that are well-optimized to execute loops and rotating register file is an example of such a component present in CGRAs. Due to the rotating nature of register indexes in rotating register file, it is very challenging, if at all possible, to hold and properly index memory addresses (pointers) and static values. In this Thesis, different structures for CGRA register files are investigated. Those structures are experimentally compared in terms of performance of mapped applications, design frequency, and area. It is shown that a register file that can logically be partitioned into rotating and non-rotating regions is an excellent choice because it imposes the minimum restriction on underlying CGRA mapping algorithm while resulting in efficient resource utilization.
Date Created
2014
Contributors
- Saluja, Dipal (Author)
- Shrivastava, Aviral (Thesis advisor)
- Lee, Yann-Hang (Committee member)
- Wu, Carole-Jean (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
vii, 30 p. : ill. (some col.)
Language
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.25844
Statement of Responsibility
Dipal Saluja
Description Source
Viewed on Nov. 18, 2014
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2014
Note type
thesis
Includes bibliographical references (p. 29-30)
Note type
bibliography
Field of study: Computer science
System Created
- 2014-10-01 05:00:01
System Modified
- 2021-08-30 01:33:21
- 2 years 8 months ago
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