An innovative radiation hardened by design flip-flop

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Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel

Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF.