ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Cao, Yu
- Creators: Rogers, Bradley
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
ContributorsAn, Pei (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2013
Description
Smoke entering a flight deck cabin has been an issue for commercial aircraft for many years. The issue for a flight crew is how to mitigate the smoke so that they can safely fly the aircraft. For this thesis, the feasibility of having a Negative Pressure System that utilizes the cabin altitude pressure and outside altitude pressure to remove smoke from a flight deck was studied. Existing procedures for flight crews call for a descent down to a safe level for depressurizing the aircraft before taking further action. This process takes crucial time that is critical to the flight crew's ability to keep aware of the situation. This process involves a flight crews coordination and fast thinking to manually take control of the aircraft; which has become increasing more difficult due to the advancements in aircraft automation. Unfortunately this is the only accepted procedure that is used by a flight crew. Other products merely displace the smoke. This displacement is after the time it takes for the flight crew to set up the smoke displacement unit with no guarantee that a flight crew will be able to see or use all of the aircraft's controls. The Negative Pressure System will work automatically and not only use similar components already found on the aircraft, but work in conjunction with the smoke detection system and pressurization system so smoke removal can begin without having to descend down to a lower altitude. In order for this system to work correctly many factors must be taken into consideration. The size of a flight deck varies from aircraft to aircraft, therefore the ability for the system to efficiently remove smoke from an aircraft is taken into consideration. For the system to be feasible on an aircraft the cost and weight must be taken into consideration as the added fuel consumption due to weight of the system may be the limiting factor for installing such a system on commercial aircraft.
ContributorsDavies, Russell (Author) / Rogers, Bradley (Thesis advisor) / Palmgren, Dale (Committee member) / Rajadas, John (Committee member) / Arizona State University (Publisher)
Created2013
Description
Photovoltaic (PV) module nameplates typically provide the module's electrical characteristics at standard test conditions (STC). The STC conditions are: irradiance of 1000 W/m2, cell temperature of 25oC and sunlight spectrum at air mass 1.5. However, modules in the field experience a wide range of environmental conditions which affect their electrical characteristics and render the nameplate data insufficient in determining a module's overall, actual field performance. To make sound technical and financial decisions, designers and investors need additional performance data to determine the energy produced by modules operating under various field conditions. The angle of incidence (AOI) of sunlight on PV modules is one of the major parameters which dictate the amount of light reaching the solar cells. The experiment was carried out at the Arizona State University- Photovoltaic Reliability Laboratory (ASU-PRL). The data obtained was processed in accordance with the IEC 61853-2 model to obtain relative optical response of the modules (response which does not include the cosine effect). The results were then compared with theoretical models for air-glass interface and also with the empirical model developed by Sandia National Laboratories. The results showed that all modules with glass as the superstrate had identical optical response and were in agreement with both the IEC 61853-2 model and other theoretical and empirical models. The performance degradation of module over years of exposure in the field is dependent upon factors such as environmental conditions, system configuration, etc. Analyzing the degradation of power and other related performance parameters over time will provide vital information regarding possible degradation rates and mechanisms of the modules. An extensive study was conducted by previous ASU-PRL students on approximately 1700 modules which have over 13 years of hot- dry climatic field condition. An analysis of the results obtained in previous ASU-PRL studies show that the major degradation in crystalline silicon modules having glass/polymer construction is encapsulant discoloration (causing short circuit current drop) and solder bond degradation (causing fill factor drop due to series resistance increase). The power degradation for crystalline silicon modules having glass/glass construction was primarily attributed to encapsulant delamination (causing open-circuit voltage drop).
ContributorsVasantha Janakeeraman, Suryanarayana (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2013
Description
The object of this study was a 26 year old residential Photovoltaic (PV) monocrystalline silicon (c-Si) power plant, called Solar One, built by developer John F. Long in Phoenix, Arizona (a hot-dry field condition). The task for Arizona State University Photovoltaic Reliability Laboratory (ASU-PRL) graduate students was to evaluate the power plant through visual inspection, electrical performance, and infrared thermography. The purpose of this evaluation was to measure and understand the extent of degradation to the system along with the identification of the failure modes in this hot-dry climatic condition. This 4000 module bipolar system was originally installed with a 200 kW DC output of PV array (17 degree fixed tilt) and an AC output of 175 kVA. The system was shown to degrade approximately at a rate of 2.3% per year with no apparent potential induced degradation (PID) effect. The power plant is made of two arrays, the north array and the south array. Due to a limited time frame to execute this large project, this work was performed by two masters students (Jonathan Belmont and Kolapo Olakonu) and the test results are presented in two masters theses. This thesis presents the results obtained on the north array and the other thesis presents the results obtained on the south array. The resulting study showed that PV module design, array configuration, vandalism, installation methods and Arizona environmental conditions have had an effect on this system's longevity and reliability. Ultimately, encapsulation browning, higher series resistance (potentially due to solder bond fatigue) and non-cell interconnect ribbon breakages outside the modules were determined to be the primary causes for the power loss.
ContributorsBelmont, Jonathan (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Henderson, Mark (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2013
Description
Potential induced degradation (PID) due to high system voltages is one of the major degradation mechanisms in photovoltaic (PV) modules, adversely affecting their performance due to the combined effects of the following factors: system voltage, superstrate/glass surface conductivity, encapsulant conductivity, silicon nitride anti-reflection coating property and interface property (glass/encapsulant; encapsulant/cell; encapsulant/backsheet). Previous studies carried out at ASU's Photovoltaic Reliability Laboratory (ASU-PRL) showed that only negative voltage bias (positive grounded systems) adversely affects the performance of commonly available crystalline silicon modules. In previous studies, the surface conductivity of the glass surface was obtained using either conductive carbon layer extending from the glass surface to the frame or humidity inside an environmental chamber. This thesis investigates the influence of glass surface conductivity disruption on PV modules. In this study, conductive carbon was applied only on the module's glass surface without extending to the frame and the surface conductivity was disrupted (no carbon layer) at 2cm distance from the periphery of frame inner edges. This study was carried out under dry heat at two different temperatures (60 °C and 85 °C) and three different negative bias voltages (-300V, -400V, and -600V). To replicate closeness to the field conditions, half of the selected modules were pre-stressed under damp heat for 1000 hours (DH 1000) and the remaining half under 200 hours of thermal cycling (TC 200). When the surface continuity was disrupted by maintaining a 2 cm gap from the frame to the edge of the conductive layer, as demonstrated in this study, the degradation was found to be absent or negligibly small even after 35 hours of negative bias at elevated temperatures. This preliminary study appears to indicate that the modules could become immune to PID losses if the continuity of the glass surface conductivity is disrupted at the inside boundary of the frame. The surface conductivity of the glass, due to water layer formation in a humid condition, close to the frame could be disrupted just by applying a water repelling (hydrophobic) but high transmittance surface coating (such as Teflon) or modifying the frame/glass edges with water repellent properties.
ContributorsTatapudi, Sai Ravi Vasista (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 90nm nodes with less than a 5% error. Voltage-controlled delay lines at 65nm and 90nm are emulated by 32nm PANDA, which successfully match important analog metrics. And at-speed emulation is achieved as well. Several other 90nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H)
ContributorsXu, Cheng (Author) / Cao, Yu (Thesis advisor) / Blain Christen, Jennifer (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT As the use of photovoltaic (PV) modules in large power plants continues to increase globally, more studies on degradation, reliability, failure modes, and mechanisms of field aged modules are needed to predict module life expectancy based on accelerated lifetime testing of PV modules. In this work, a 26+ year old PV power plant in Phoenix, Arizona has been evaluated for performance, reliability, and durability. The PV power plant, called Solar One, is owned and operated by John F. Long's homeowners association. It is a 200 kWdc, standard test conditions (STC) rated power plant comprised of 4000 PV modules or frameless laminates, in 100 panel groups (rated at 175 kWac). The power plant is made of two center-tapped bipolar arrays, the north array and the south array. Due to a limited time frame to execute this large project, this work was performed by two masters students (Jonathan Belmont and Kolapo Olakonu) and the test results are presented in two masters theses. This thesis presents the results obtained on the south array and the other thesis presents the results obtained on the north array. Each of these two arrays is made of four sub arrays, the east sub arrays (positive and negative polarities) and the west sub arrays (positive and negative polarities), making up eight sub arrays. The evaluation and analyses of the power plant included in this thesis consists of: visual inspection, electrical performance measurements, and infrared thermography. A possible presence of potential induced degradation (PID) due to potential difference between ground and strings was also investigated. Some installation practices were also studied and found to contribute to the power loss observed in this investigation. The power output measured in 2011 for all eight sub arrays at STC is approximately 76 kWdc and represents a power loss of 62% (from 200 kW to 76 kW) over 26+ years. The 2011 measured power output for the four south sub arrays at STC is 39 kWdc and represents a power loss of 61% (from 100 kW to 39 kW) over 26+ years. Encapsulation browning and non-cell interconnect ribbon breakages were determined to be the primary causes for the power loss.
ContributorsOlakonu, Kolapo (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
While the piezoelectric effect has been around for some time, it has only recently caught interest as a potential sustainable energy harvesting device. Piezoelectric energy harvesting has been developed for shoes and panels, but has yet to be integrated into a marketable bicycle tire. For this thesis, the development and feasibility of a piezoelectric tire was done. This includes the development of a circuit that incorporates piezoceramic elements, energy harvesting circuitry, and an energy storage device. A single phase circuit was designed using an ac-dc diode rectifier. An electrolytic capacitor was used as the energy storage device. A financial feasibility was also done to determine targets for manufacturing cost and sales price. These models take into account market trends for high performance tires, economies of scale, and the possibility of government subsidies. This research will help understand the potential for the marketability of a piezoelectric energy harvesting tire that can create electricity for remote use. This study found that there are many obstacles that must be addressed before a piezoelectric tire can be marketed to the general public. The power output of this device is miniscule compared to an alkaline battery. In order for this device to approach the power output of an alkaline battery the weight of the device would also become an issue. Additionally this device is very costly compared to the average bicycle tire. Lastly, this device is extreme fragile and easily broken. In order for this device to become marketable the issues of power output, cost, weight, and durability must all be successfully overcome.
ContributorsMalotte, Christopher (Author) / Madakannan, Arunachalanadar (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012