ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 84
Description
This research examines the current challenges of using Lamb wave interrogation methods to localize fatigue crack damage in a complex metallic structural component subjected to unknown temperatures. The goal of this work is to improve damage localization results for a structural component interrogated at an unknown temperature, by developing a probabilistic and reference-free framework for estimating Lamb wave velocities and the damage location. The methodology for damage localization at unknown temperatures includes the following key elements: i) a model that can describe the change in Lamb wave velocities with temperature; ii) the extension of an advanced time-frequency based signal processing technique for enhanced time-of-flight feature extraction from a dispersive signal; iii) the development of a Bayesian damage localization framework incorporating data association and sensor fusion. The technique requires no additional transducers to be installed on a structure, and allows for the estimation of both the temperature and the wave velocity in the component. Additionally, the framework of the algorithm allows it to function completely in an unsupervised manner by probabilistically accounting for all measurement origin uncertainty. The novel algorithm was experimentally validated using an aluminum lug joint with a growing fatigue crack. The lug joint was interrogated using piezoelectric transducers at multiple fatigue crack lengths, and at temperatures between 20°C and 80°C. The results showed that the algorithm could accurately predict the temperature and wave speed of the lug joint. The localization results for the fatigue damage were found to correlate well with the true locations at long crack lengths, but loss of accuracy was observed in localizing small cracks due to time-of-flight measurement errors. To validate the algorithm across a wider range of temperatures the electromechanically coupled LISA/SIM model was used to simulate the effects of temperatures. The numerical results showed that this approach would be capable of experimentally estimating the temperature and velocity in the lug joint for temperatures from -60°C to 150°C. The velocity estimation algorithm was found to significantly increase the accuracy of localization at temperatures above 120°C when error due to incorrect velocity selection begins to outweigh the error due to time-of-flight measurements.
ContributorsHensberry, Kevin (Author) / Chattopadhyay, Aditi (Thesis advisor) / Liu, Yongming (Committee member) / Papandreou-Suppappola, Antonia (Committee member) / Arizona State University (Publisher)
Created2013
Description
Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply
ContributorsKundur, Vinay (Author) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Aluminum alloys and their composites are attractive materials for applications requiring high strength-to-weight ratios and reasonable cost. Many of these applications, such as those in the aerospace industry, undergo fatigue loading. An understanding of the microstructural damage that occurs in these materials is critical in assessing their fatigue resistance. Two distinct experimental studies were performed to further the understanding of fatigue damage mechanisms in aluminum alloys and their composites, specifically fracture and plasticity. Fatigue resistance of metal matrix composites (MMCs) depends on many aspects of composite microstructure. Fatigue crack growth behavior is particularly dependent on the reinforcement characteristics and matrix microstructure. The goal of this work was to obtain a fundamental understanding of fatigue crack growth behavior in SiC particle-reinforced 2080 Al alloy composites. In situ X-ray synchrotron tomography was performed on two samples at low (R=0.1) and at high (R=0.6) R-ratios. The resulting reconstructed images were used to obtain three-dimensional (3D) rendering of the particles and fatigue crack. Behaviors of the particles and crack, as well as their interaction, were analyzed and quantified. Four-dimensional (4D) visual representations were constructed to aid in the overall understanding of damage evolution. During fatigue crack growth in ductile materials, a plastic zone is created in the region surrounding the crack tip. Knowledge of the plastic zone is important for the understanding of fatigue crack formation as well as subsequent growth behavior. The goal of this work was to quantify the 3D size and shape of the plastic zone in 7075 Al alloys. X-ray synchrotron tomography and Laue microdiffraction were used to non-destructively characterize the volume surrounding a fatigue crack tip. The precise 3D crack profile was segmented from the reconstructed tomography data. Depth-resolved Laue patterns were obtained using differential-aperture X-ray structural microscopy (DAXM), from which peak-broadening characteristics were quantified. Plasticity, as determined by the broadening of diffracted peaks, was mapped in 3D. Two-dimensional (2D) maps of plasticity were directly compared to the corresponding tomography slices. A 3D representation of the plastic zone surrounding the fatigue crack was generated by superimposing the mapped plasticity on the 3D crack profile.
ContributorsHruby, Peter (Author) / Chawla, Nikhilesh (Thesis advisor) / Solanki, Kiran (Committee member) / Liu, Yongming (Committee member) / Arizona State University (Publisher)
Created2014
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
This research focuses on the benefits of using nanocomposites in aerospace structural components to prevent or delay the onset of unique composite failure modes, such as delamination. Analytical, numerical, and experimental analyses were conducted to provide a comprehensive understanding of how carbon nanotubes (CNTs) can provide additional structural integrity when they are used in specific hot spots within a structure. A multiscale approach was implemented to determine the mechanical and thermal properties of the nanocomposites, which were used in detailed finite element models (FEMs) to analyze interlaminar failures in T and Hat section stringers. The delamination that first occurs between the tow filler and the bondline between the stringer and skin was of particular interest. Both locations are considered to be hot spots in such structural components, and failures tend to initiate from these areas. In this research, nanocomposite use was investigated as an alternative to traditional methods of suppressing delamination. The stringer was analyzed under different loading conditions and assuming different structural defects. Initial damage, defined as the first drop in the load displacement curve was considered to be a useful variable to compare the different behaviors in this study and was detected via the virtual crack closure technique (VCCT) implemented in the FE analysis.
Experiments were conducted to test T section skin/stringer specimens under pull-off loading, replicating those used in composite panels as stiffeners. Two types of designs were considered: one using pure epoxy to fill the tow region and another that used nanocomposite with 5 wt. % CNTs. The response variable in the tests was the initial damage. Detailed analyses were conducted using FEMs to correlate with the experimental data. The correlation between both the experiment and model was satisfactory. Finally, the effects of thermal cure and temperature variation on nanocomposite structure behavior were studied, and both variables were determined to influence the nanocomposite structure performance.
Experiments were conducted to test T section skin/stringer specimens under pull-off loading, replicating those used in composite panels as stiffeners. Two types of designs were considered: one using pure epoxy to fill the tow region and another that used nanocomposite with 5 wt. % CNTs. The response variable in the tests was the initial damage. Detailed analyses were conducted using FEMs to correlate with the experimental data. The correlation between both the experiment and model was satisfactory. Finally, the effects of thermal cure and temperature variation on nanocomposite structure behavior were studied, and both variables were determined to influence the nanocomposite structure performance.
ContributorsHasan, Zeaid (Author) / Chattopadhyay, Aditi (Thesis advisor) / Dai, Lenore (Committee member) / Jiang, Hanqing (Committee member) / Rajadas, John (Committee member) / Liu, Yongming (Committee member) / Arizona State University (Publisher)
Created2014
Description
Mobile platforms are becoming highly heterogeneous by combining a powerful multiprocessor system-on-chip (MpSoC) with numerous resources including display, memory, power management IC (PMIC), battery and wireless modems into a compact package. Furthermore, the MpSoC itself is a heterogeneous resource that integrates many processing elements such as CPU cores, GPU, video, image, and audio processors. As a result, optimization approaches targeting mobile computing needs to consider the platform at various levels of granularity.
Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. In this work, the models for power consumption, response time, and energy consumption of heterogeneous mobile platforms are presented. Then, these models are used to optimize the energy consumption of baseline platforms under power, response time, and temperature constraints with and without introducing new resources. It is shown, the optimal design choices depend on dynamic power management algorithm, and adding new resources is more energy efficient than scaling existing resources alone. The framework is verified through actual experiments on Qualcomm Snapdragon 800 based tablet MDP/T. Furthermore, usage of the framework at both design and runtime optimization is also presented.
Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. In this work, the models for power consumption, response time, and energy consumption of heterogeneous mobile platforms are presented. Then, these models are used to optimize the energy consumption of baseline platforms under power, response time, and temperature constraints with and without introducing new resources. It is shown, the optimal design choices depend on dynamic power management algorithm, and adding new resources is more energy efficient than scaling existing resources alone. The framework is verified through actual experiments on Qualcomm Snapdragon 800 based tablet MDP/T. Furthermore, usage of the framework at both design and runtime optimization is also presented.
ContributorsGupta, Ujjwala (Author) / Ogras, Umit Y. (Thesis advisor) / Ozev, Sule (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2014
Description
In this dissertation, the results of our comprehensive computational studies of disordered jammed (i.e., mechanically stable) packings of hard particles are presented, including the family of superdisks in 2D and ellipsoids in 3D Euclidean space. Following a very brief introduction to the hard-particle systems, the event driven molecular dynamics (EDMD) employed to generate the packing ensembles will be discussed. A large number of 2D packing configurations of superdisks are subsequently analyzed, through which a relatively accurate theoretical scheme for packing-fraction prediction based on local particle contact configurations is proposed and validated via additional numerical simulations. Moreover, the studies on binary ellipsoid packing in 3D are briefly discussed and the effects of different geometrical parameters on the final packing fraction are analyzed.
ContributorsXu, Yaopengxiao (Author) / Jiao, Yang (Thesis advisor) / Oswald, Jay (Committee member) / Liu, Yongming (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
The focus of this investigation is on the formulation and a validation of reduced order models (ROMs) for the prediction of the response of structures with embedded piezoelectric actuators. The ROMs considered here are those constructed in a nonintrusive manner from a commercial finite element software, NASTRAN is adopted here. Notwithstanding the popularity of piezoelectric materials in structural dynamics related applications such as structural health monitoring and energy harvesting, not all commercial finite element software allow directly their modeling. In such cases, e.g., with NASTRAN, one can proceed with an analogy and replace the electric actuation in the piezoelectric material by a fictitious thermal effect producing the same strain. This process recasts the determination of a ROM for a structure with embedded piezoelectric actuator into a similar ROM but for a heated structure, the framework of which has recently been developed. Yet, the temperature field resulting from the analogy would be quite different from the one considered in past effort and would excite a broad array of structural modes. Accordingly, as a preamble to considering a beam with a piezoelectric layer, a simpler plate model is considered that is subjected to a uniform temperature but a complex pressure loading that excites the entire set of modes of the plate in the broad frequency band considered. The very good match of the predictions obtained by this ROM in comparison to their full finite element counterparts provides the necessary confidence to next address a beam with embedded piezoelectic actuator. The test model considered for this validation is a built-up nano beam analyzed recently in nonlinear geometric conditions by full finite elements and by a non-intrusive ROM procedure under harmonic variations of the piezoelectic voltage. This structural model and its loading conditions are very different from those considered in past applications of nonintrusive ROMs, thus the excellent results obtained here provide further support of the broad generality of the nonintrusive ROM methodology, including of the appropriateness of the "dual modes" basis functions.
ContributorsVyas, Varun (Author) / Mignolet, Marc (Thesis advisor) / Hollkamp, Joseph (Committee member) / Liu, Yongming (Committee member) / Arizona State University (Publisher)
Created2014
Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011