ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 15
Filtering by
- Creators: Ayyanar, Raja
Description
The dissertation encompasses the transformer-less single phase PV inverters for both the string and microinverter applications. Two of the major challenge with such inverters include the presence of high-frequency common mode leakage current and double line frequency power decoupling with reliable capacitors without compromising converter power density. Two solutions are presented in this dissertation: half-bridge voltage swing (HBVS) and dynamic dc link (DDCL) inverters both of which completely eliminates the ground current through topological improvement. In addition, through active power decoupling technique, the capacitance requirement is reduced for both, thus achieving an all film-capacitor based solution with higher reliability. Also both the approaches are capable of supporting a wide range of power factor.
Moreover, wide band-gap devices (both SiC and GaN) are used for implementing their hardware prototypes. It enables the switching frequency to be high without compromising on the converter efficiency. Also it allows a reduced magnetic component size, further enabling a high power density solution, with power density far beyond the state-of-the art solutions.
Additionally, for the transformer-less microinverter application, another challenge is to achieve a very high gain DC-DC stage with a simultaneous high conversion efficiency. An extended duty ratio (EDR) boost converter which is a hybrid of switched capacitors and interleaved inductor technique, has been implemented for this purpose. It offers higher converter efficiency as most of the switches encounter lower voltage stress directly impacting switching loss; the input current being shared among all the interleaved converters (inherent sharing only in a limited duty ratio), the inductor conduction loss is reduced by a factor of the number of phases.
Further, the EDR boost converter has been studied for both discontinuous conduction mode (DCM) operations and operations with wide input/output voltage range in continuous conduction mode (CCM). A current sharing between its interleaved input phases is studied in detail to show that inherent sharing is possible for only in a limited duty ratio span, and modification of the duty ratio scheme is proposed to ensure equal current sharing over all the operating range for 3 phase EDR boost. All the analysis are validated with experimental results.
Moreover, wide band-gap devices (both SiC and GaN) are used for implementing their hardware prototypes. It enables the switching frequency to be high without compromising on the converter efficiency. Also it allows a reduced magnetic component size, further enabling a high power density solution, with power density far beyond the state-of-the art solutions.
Additionally, for the transformer-less microinverter application, another challenge is to achieve a very high gain DC-DC stage with a simultaneous high conversion efficiency. An extended duty ratio (EDR) boost converter which is a hybrid of switched capacitors and interleaved inductor technique, has been implemented for this purpose. It offers higher converter efficiency as most of the switches encounter lower voltage stress directly impacting switching loss; the input current being shared among all the interleaved converters (inherent sharing only in a limited duty ratio), the inductor conduction loss is reduced by a factor of the number of phases.
Further, the EDR boost converter has been studied for both discontinuous conduction mode (DCM) operations and operations with wide input/output voltage range in continuous conduction mode (CCM). A current sharing between its interleaved input phases is studied in detail to show that inherent sharing is possible for only in a limited duty ratio span, and modification of the duty ratio scheme is proposed to ensure equal current sharing over all the operating range for 3 phase EDR boost. All the analysis are validated with experimental results.
ContributorsRoy, Jinia (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2017
Description
The growth of energy demands in recent years has been increasing faster than the expansion of transmission facility construction. This tendency cooperating with the continuous investing on the renewable energy resources drives the research, development, and construction of HVDC projects to create a more reliable, affordable, and environmentally friendly power grid.
Constructing the hybrid AC-HVDC grid is a significant move in the development of the HVDC techniques; the form of dc system is evolving from the point-to-point stand-alone dc links to the embedded HVDC system and the multi-terminal HVDC (MTDC) system. The MTDC is a solution for the renewable energy interconnections, and the MTDC grids can improve the power system reliability, flexibility in economic dispatches, and converter/cable utilizing efficiencies.
The dissertation reviews the HVDC technologies, discusses the stability issues regarding the ac and HVDC connections, proposes a novel power oscillation control strategy to improve system stability, and develops a nonlinear voltage droop control strategy for the MTDC grid.
To verify the effectiveness the proposed power oscillation control strategy, a long distance paralleled AC-HVDC transmission test system is employed. Based on the PSCAD/EMTDC platform simulation results, the proposed power oscillation control strategy can improve the system dynamic performance and attenuate the power oscillations effectively.
To validate the nonlinear voltage droop control strategy, three droop controls schemes are designed according to the proposed nonlinear voltage droop control design procedures. These control schemes are tested in a hybrid AC-MTDC system. The hybrid AC-MTDC system, which is first proposed in this dissertation, consists of two ac grids, two wind farms and a five-terminal HVDC grid connecting them. Simulation studies are performed in the PSCAD/EMTDC platform. According to the simulation results, all the three design schemes have their unique salient features.
Constructing the hybrid AC-HVDC grid is a significant move in the development of the HVDC techniques; the form of dc system is evolving from the point-to-point stand-alone dc links to the embedded HVDC system and the multi-terminal HVDC (MTDC) system. The MTDC is a solution for the renewable energy interconnections, and the MTDC grids can improve the power system reliability, flexibility in economic dispatches, and converter/cable utilizing efficiencies.
The dissertation reviews the HVDC technologies, discusses the stability issues regarding the ac and HVDC connections, proposes a novel power oscillation control strategy to improve system stability, and develops a nonlinear voltage droop control strategy for the MTDC grid.
To verify the effectiveness the proposed power oscillation control strategy, a long distance paralleled AC-HVDC transmission test system is employed. Based on the PSCAD/EMTDC platform simulation results, the proposed power oscillation control strategy can improve the system dynamic performance and attenuate the power oscillations effectively.
To validate the nonlinear voltage droop control strategy, three droop controls schemes are designed according to the proposed nonlinear voltage droop control design procedures. These control schemes are tested in a hybrid AC-MTDC system. The hybrid AC-MTDC system, which is first proposed in this dissertation, consists of two ac grids, two wind farms and a five-terminal HVDC grid connecting them. Simulation studies are performed in the PSCAD/EMTDC platform. According to the simulation results, all the three design schemes have their unique salient features.
ContributorsYu, Jicheng (Author) / Karady, George G. (Thesis advisor, Committee member) / Qin, Jiangchao (Thesis advisor, Committee member) / Ayyanar, Raja (Committee member) / Holbert, Keith E. (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2017
Description
The following report details the motivation, design, analysis, simulation and hardware implementation of a DC/DC converter in EV drivetrain architectures. The primary objective of the project was to improve overall system efficiency in an EV drivetrain. The methodology employed to this end required a variable or flexible DC-Link voltage at the input of the inverter stage. Amongst the several advantages associated with such a system are the independent optimization of the battery stack and the inverter over a wide range of motor operating conditions. The incorporation of a DC/DC converter into the drivetrain helps lower system losses but since it is an additional component, a number of considerations need to be made during its design. These include stringent requirements on power density, converter efficiency and reliability.
These targets for the converter are met through a number of different ways. The switches used are Silicon Carbide FETs. These are wide band gap (WBG) devices that can operate at high frequencies and temperatures. Since they allow for high frequency operation, a switching frequency of 250 khz is proposed and implemented. This helps with power density by reducing the size of passive components. High efficiencies are made possible by using a simple soft switching technique by augmenting the DC/DC converter with an auxiliary branch to enable zero voltage transition.
The efficacy of the approach is tested through simulation and hardware implementation of two different prototypes. The Gen-I prototype was a single soft switched synchronous boost converter rated at 2.5kw. Both the motoring mode and regenerative modes of operation (Boost and Buck) were hardware tested for over 2kw and efficiency results of over 98.15% were achieved. The Gen-II prototype and the main focus of this work is an interleaved soft switched synchronous boost converter. This converter has been implemented in hardware as well and has been tested at 6.7kw and an efficiency of over 98% has been achieved in the boost mode of operation.
These targets for the converter are met through a number of different ways. The switches used are Silicon Carbide FETs. These are wide band gap (WBG) devices that can operate at high frequencies and temperatures. Since they allow for high frequency operation, a switching frequency of 250 khz is proposed and implemented. This helps with power density by reducing the size of passive components. High efficiencies are made possible by using a simple soft switching technique by augmenting the DC/DC converter with an auxiliary branch to enable zero voltage transition.
The efficacy of the approach is tested through simulation and hardware implementation of two different prototypes. The Gen-I prototype was a single soft switched synchronous boost converter rated at 2.5kw. Both the motoring mode and regenerative modes of operation (Boost and Buck) were hardware tested for over 2kw and efficiency results of over 98.15% were achieved. The Gen-II prototype and the main focus of this work is an interleaved soft switched synchronous boost converter. This converter has been implemented in hardware as well and has been tested at 6.7kw and an efficiency of over 98% has been achieved in the boost mode of operation.
ContributorsRaza, Bassam (Author) / Ayyanar, Raja (Thesis advisor) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Prior work in literature has illustrated the benefits of using surge arrester as a way to improve the lighting performance of the substation and transmission line. Installing surge arresters would enhance the system reliability but it comes with an extra capital expenditure. This thesis provides simulation analysis to examine substation-specific applications of surge arrester as a way of determining the optimal, cost-effective placement of surge arresters. Four different surge arrester installation configurations are examined for the 500/230 kV Rudd substation which belongs to the utility, Salt River Project (SRP). The most efficient configuration is identified in this thesis. A new method “voltage-distance curve” is proposed in this work to evaluate different surge arrester installation configurations. Simulation results show that surge arresters only need to be equipped on certain location of the substation and can still ensure sufficient lightning protection.
With lower tower footing resistance, the lightning performance of the transmission line can typically be improved. However, when surge arresters are installed in the system, the footing resistance may have either negative or positive effect on the lightning performance. Different situations for both effects are studied in this thesis.
This thesis proposes a surge arrester installation strategy for the overhead transmission line lightning protection. In order to determine the most efficient surge arrester configuration of transmission line, the entire transmission line is divided into several line sections according to the footing resistance of its towers. A line section consists of the towers which have similar footing resistance. Two different designs are considered for transmission line lightning protection, they include: equip different number of surge arrester on selected phase of every tower, equip surge arresters on all phases of selected towers. By varying the number of the towers or the number of phases needs to be equipped with surge arresters, the threshold voltage for line insulator flashover is used to evaluate different surge arrester installation configurations. The way to determine the optimal surge arresters configuration for each line section is then introduced in this thesis.
With lower tower footing resistance, the lightning performance of the transmission line can typically be improved. However, when surge arresters are installed in the system, the footing resistance may have either negative or positive effect on the lightning performance. Different situations for both effects are studied in this thesis.
This thesis proposes a surge arrester installation strategy for the overhead transmission line lightning protection. In order to determine the most efficient surge arrester configuration of transmission line, the entire transmission line is divided into several line sections according to the footing resistance of its towers. A line section consists of the towers which have similar footing resistance. Two different designs are considered for transmission line lightning protection, they include: equip different number of surge arrester on selected phase of every tower, equip surge arresters on all phases of selected towers. By varying the number of the towers or the number of phases needs to be equipped with surge arresters, the threshold voltage for line insulator flashover is used to evaluate different surge arrester installation configurations. The way to determine the optimal surge arresters configuration for each line section is then introduced in this thesis.
ContributorsXia, Qianxue (Author) / Karady, George G. (Thesis advisor) / Ayyanar, Raja (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2018
Description
The most important metrics considered for electric vehicles are power density, efficiency, and reliability of the powertrain modules. The powertrain comprises of an Electric Machine (EM), power electronic converters, an Energy Management System (EMS), and an Energy Storage System (ESS). The power electronic converters are used to couple the motor with the battery stack. Including a DC/DC converter in the powertrain module is favored as it adds an additional degree of freedom to achieve flexibility in optimizing the battery module and inverter independently. However, it is essential that the converter is rated for high peak power and can maintain high efficiency while operating over a wide range of load conditions to not compromise on system efficiency. Additionally, the converter must strictly adhere to all automotive standards.
Currently, several hard-switching topologies have been employed such as conventional boost DC/DC, interleaved step-up DC/DC, and full-bridge DC/DC converter. These converters face respective limitations in achieving high step-up conversion ratio, size and weight issues, or high component count. In this work, a bi-directional synchronous boost DC/DC converter with easy interleaving capability is proposed with a novel ZVT mechanism. This converter steps up the EV battery voltage of 200V-300V to a wide range of variable output voltages ranging from 310V-800V. High power density and efficiency are achieved through high switching frequency of 250kHz for each phase with effective frequency doubling through interleaving. Also, use of wide bandgap high voltage SiC switches allows high efficiency operation even at high temperatures.
Comprehensive analysis, design details and extensive simulation results are presented. Incorporating ZVT branch with adaptive time delay results in converter efficiency close to 98%. Experimental results from a 2.5kW hardware prototype validate the performance of the proposed approach. A peak efficiency of 98.17% has been observed in hardware in the boost or motoring mode.
Currently, several hard-switching topologies have been employed such as conventional boost DC/DC, interleaved step-up DC/DC, and full-bridge DC/DC converter. These converters face respective limitations in achieving high step-up conversion ratio, size and weight issues, or high component count. In this work, a bi-directional synchronous boost DC/DC converter with easy interleaving capability is proposed with a novel ZVT mechanism. This converter steps up the EV battery voltage of 200V-300V to a wide range of variable output voltages ranging from 310V-800V. High power density and efficiency are achieved through high switching frequency of 250kHz for each phase with effective frequency doubling through interleaving. Also, use of wide bandgap high voltage SiC switches allows high efficiency operation even at high temperatures.
Comprehensive analysis, design details and extensive simulation results are presented. Incorporating ZVT branch with adaptive time delay results in converter efficiency close to 98%. Experimental results from a 2.5kW hardware prototype validate the performance of the proposed approach. A peak efficiency of 98.17% has been observed in hardware in the boost or motoring mode.
ContributorsMullangi Chenchu, Hemanth (Author) / Ayyanar, Raja (Thesis advisor) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2018
Description
With the increasing penetration of Photovoltaic inverters, there is a necessity for recent PV inverters to have smart grid support features for increased power system reliability and security. The grid support features include voltage support, active and reactive power control. These support features mean that inverters should have bidirectional power and communication capabilities. The inverter should be able to communicate with the grid utility and other inverter modules.
This thesis studies the real time simulation of smart inverters using PLECS Real Time Box. The real time simulation is performed as a Controller Hardware in the Loop (CHIL) real time simulation. In this thesis, the power stage of the smart inverter is emulated in the PLECS Real Time Box and the controller stage of the inverter is programmed in the Digital Signal Processor (DSP) connected to the real time box. The power stage emulated in the real time box and the controller implemented in the DSP form a closed loop smart inverter.
This smart inverter, with power stage and controller together, is then connected to an OPAL-RT simulator which emulates the power distribution system of the Arizona State University Poly campus. The smart inverter then sends and receives commands to supply power and support the grid. The results of the smart inverter with the PLECS Real time box and the smart inverter connected to an emulated distribution system are discussed under various conditions based on the commands received by the smart inverter.
This thesis studies the real time simulation of smart inverters using PLECS Real Time Box. The real time simulation is performed as a Controller Hardware in the Loop (CHIL) real time simulation. In this thesis, the power stage of the smart inverter is emulated in the PLECS Real Time Box and the controller stage of the inverter is programmed in the Digital Signal Processor (DSP) connected to the real time box. The power stage emulated in the real time box and the controller implemented in the DSP form a closed loop smart inverter.
This smart inverter, with power stage and controller together, is then connected to an OPAL-RT simulator which emulates the power distribution system of the Arizona State University Poly campus. The smart inverter then sends and receives commands to supply power and support the grid. The results of the smart inverter with the PLECS Real time box and the smart inverter connected to an emulated distribution system are discussed under various conditions based on the commands received by the smart inverter.
ContributorsThiagarajan, Ramanathan (Author) / Ayyanar, Raja (Thesis advisor) / Lei, Qin (Committee member) / Qin, Jiangchao (Committee member) / Arizona State University (Publisher)
Created2017
Description
Two major challenges in the transformer-less, single-phase PV string inverters are common mode leakage currents and double-line-frequency power decoupling. In the proposed doubly-grounded inverter topology with innovative active-power-decoupling approach, both of these issues are simultaneously addressed. The topology allows the PV negative terminal to be directly connected to the neutral, thereby eliminating the common-mode ground-currents. The decoupling capacitance requirement is minimized by a dynamically-variable dc-link with large voltage swing, allowing an all-film-capacitor implementation. Furthermore, the use of wide-bandgap devices enables the converter operation at higher switching frequency, resulting in smaller magnetic components. The operating principles, design and optimization, and control methods are explained in detail, and compared with other transformer-less, active-decoupling topologies. A 3 kVA, 100 kHz single-phase hardware prototype at 400 V dc nominal input and 240 V ac output has been developed using SiC MOSFETs with only 45 μF/1100 V dc-link capacitance. The proposed doubly-grounded topology is then extended for split-phase PV inverter application which results in significant reduction in both the peak and RMS values of the boost stage inductor current and allows for easy design of zero voltage transition. A topological enhancement involving T-type dc-ac stage is also developed which takes advantage of the three-level switching states with reduced voltage stress on the main switches, lower switching loss and almost halved inductor current ripple.
In addition, this thesis also proposed two new schemes to improve the efficiency of conventional H-bridge inverter topology. The first scheme is to add an auxiliary zero-voltage-transition (ZVT) circuit to realize zero-voltage-switching (ZVS) for all the main switches and inherent zero-current-switching (ZCS) for the auxiliary switches. The advantages include the provision to implement zero state modulation schemes to decrease the inductor current THD, naturally adaptive auxiliary inductor current and elimination of need for large balancing capacitors. The second proposed scheme improves the system efficiency while still meeting a given THD requirement by implementing variable instantaneous switching frequency within a line frequency cycle. This scheme aims at minimizing the combined switching loss and inductor core loss by including different characteristics of the losses relative to the instantaneous switching frequency in the optimization process.
In addition, this thesis also proposed two new schemes to improve the efficiency of conventional H-bridge inverter topology. The first scheme is to add an auxiliary zero-voltage-transition (ZVT) circuit to realize zero-voltage-switching (ZVS) for all the main switches and inherent zero-current-switching (ZCS) for the auxiliary switches. The advantages include the provision to implement zero state modulation schemes to decrease the inductor current THD, naturally adaptive auxiliary inductor current and elimination of need for large balancing capacitors. The second proposed scheme improves the system efficiency while still meeting a given THD requirement by implementing variable instantaneous switching frequency within a line frequency cycle. This scheme aims at minimizing the combined switching loss and inductor core loss by including different characteristics of the losses relative to the instantaneous switching frequency in the optimization process.
ContributorsXia, Yinglai (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Lei, Qin (Committee member) / Qin, Jiangchao (Committee member) / Arizona State University (Publisher)
Created2017
Description
This thesis investigates different unidirectional topologies for the on-board charger in an electric vehicle and proposes soft-switching solutions in both the AC/DC and DC/DC stage of the converter with a power rating of 3.3 kW. With an overview on different charger topologies and their applicability with respect to the target specification a soft-switching technique to reduce the switching losses of a single phase boost-type PFC is proposed. This work is followed by a modification to the popular soft-switching topology, the dual active bridge (DAB) converter for application requiring unidirectional power flow. The topology named as the semi-dual active bridge (S-DAB) is obtained by replacing the fully active (four switches) bridge on the load side of a DAB by a semi-active (two switches and two diodes) bridge. The operating principles, waveforms in different intervals and expression for power transfer, which differ significantly from the basic DAB topology, are presented in detail. The zero-voltage switching (ZVS) characteristics and requirements are analyzed in detail and compared to those of DAB. A small-signal model of the new configuration is also derived. The analysis and performance of S-DAB are validated through extensive simulation and experimental results from a hardware prototype.
Secondly, a low-loss auxiliary circuit for a power factor correction (PFC) circuit to achieve zero voltage transition is also proposed to improve the efficiency and operating frequency of the converter. The high dynamic energy generated in the switching node during turn-on is diverted by providing a parallel path through an auxiliary inductor and a transistor placed across the main inductor. The paper discusses the operating principles, design, and merits of the proposed scheme with hardware validation on a 3.3 kW/ 500 kHz PFC prototype. Modifications to the proposed zero voltage transition (ZVT) circuit is also investigated by implementing two topological variations. Firstly, an integrated magnetic structure is built combining the main inductor and auxiliary inductor in a single core reducing the total footprint of the circuit board. This improvement also reduces the size of the auxiliary capacitor required in the ZVT operation. The second modification redirects the ZVT energy from the input end to the DC link through additional half-bridge circuit and inductor. The half-bridge operating at constant 50% duty cycle simulates a switching leg of the following DC/DC stage of the converter. A hardware prototype of the above-mentioned PFC and DC/DC stage was developed and the operating principles were verified using the same.
Secondly, a low-loss auxiliary circuit for a power factor correction (PFC) circuit to achieve zero voltage transition is also proposed to improve the efficiency and operating frequency of the converter. The high dynamic energy generated in the switching node during turn-on is diverted by providing a parallel path through an auxiliary inductor and a transistor placed across the main inductor. The paper discusses the operating principles, design, and merits of the proposed scheme with hardware validation on a 3.3 kW/ 500 kHz PFC prototype. Modifications to the proposed zero voltage transition (ZVT) circuit is also investigated by implementing two topological variations. Firstly, an integrated magnetic structure is built combining the main inductor and auxiliary inductor in a single core reducing the total footprint of the circuit board. This improvement also reduces the size of the auxiliary capacitor required in the ZVT operation. The second modification redirects the ZVT energy from the input end to the DC link through additional half-bridge circuit and inductor. The half-bridge operating at constant 50% duty cycle simulates a switching leg of the following DC/DC stage of the converter. A hardware prototype of the above-mentioned PFC and DC/DC stage was developed and the operating principles were verified using the same.
ContributorsKulasekaran, Siddharth (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2017
Description
Voltage Source Inverter (VSI) is an integral component that converts DC voltage to AC voltage suitable for driving the electric motor in Electric Vehicles/Hybrid Electric Vehicles (EVs/HEVs) and integration with electric grid in grid-connected photovoltaic (PV) converter. Performance of VSI is significantly impacted by the type of Pulse Width Modulation (PWM) method used.In this work, a new PWM method called 240° Clamped Space Vector PWM (240CPWM) is studied extensively. 240CPWM method has the major advantages of clamping a phase to the positive or negative rail for 240° in a fundamental period, clamping of two phases simultaneously at any given instant, and use of only active states, completely eliminating the zero states. These characteristics lead to a significant reduction in switching losses of the inverter and lower DC link capacitor current stress as compared to Conventional Space Vector PWM. A unique six pulse dynamically varying DC link voltage is required for 240CPWM instead of constant DC link voltage to maintain sinusoidal output voltage. Voltage mode control of DC-DC stage with Smith predictor is developed for shaping the dynamic DC link voltage that meets the requirements for fast control.
Experimental results from a 10 kW hardware prototype with 10 kHz switching frequency validate the superior performance of 240CPWM in EV/HEV traction inverters focusing on loss reduction and DC link capacitor currents. Full load efficiency with the proposed 240CPWM for the DC-AC stage even with conventional Silicon devices exceeds 99%.
Performance of 240CPWM is evaluated in three phase grid-connected PV converter. It is verified experimentally that 240CPWM performs well under adverse grid conditions like sag/swell and unbalance in grid voltages, and under a wide range of power factor. Undesired low frequency harmonics in inverter currents are minimized using the Harmonic Compensator that results in Total Harmonic Distortion (THD) of 3.5% with 240CPWM in compliance with grid interconnection standards. A new, combined performance index is proposed to compare the performance of different PWM schemes in terms of switching loss, THD, DC link current stress, Common Mode Voltage and leakage current. 240CPWM achieves the best value for this index among the PWM methods studied.
ContributorsQamar, Haleema (Author) / Ayyanar, Raja (Thesis advisor) / Yu, Hongbin (Committee member) / Lei, Qin (Committee member) / Weng, Yang (Committee member) / Arizona State University (Publisher)
Created2022
Description
The performance of voltage source inverter (VSI) in terms of output waveform quality, conversion efficiency and common mode noise depends greatly on the pulse width modulation (PWM) method. In this work, a low-loss space vector PWM i.e., 240°-clamped space vector PWM (240CPWM) is proposed to improve the performance of VSIs in electric/hybrid electric vehicles (EV/HEVs) and grid connected photovoltaic (PV) systems. The salient features of 240CPWM include 240° clamping of each phase pole to positive or negative DC bus in a fundamental cycle ensuring that switching losses are reduced by a factor of seven as compared to conventional space vector PWM (CSVPWM) at unity power factor. Zero states are completely eliminated and only two nearest active states are used ensuring that there is no penalty in terms of total harmonic distortion (THD) in line current. The THD of the line current is analyzed using the notion of stator flux ripple and compared with conventional and discontinuous PWM method. Discontinuous PWM methods achieve switching loss reduction at the expense of higher THD while 240CPWM achieves a much greater loss reduction without impacting the THD. The analysis and performance of 240CPWM are validated on a 10 kW two-stage experimental prototype.
Common mode voltage (CMV) and leakage current characteristics of 240CPWM are analyzed in detail. It is shown analytically that 240CPWM reduces the CMV and leakage current as compared to other PWM methods while simultaneously reducing the switching loss and THD. Experimental results from a 10-kW hardware prototype conform to the analytical discussions and validate the superior performance of 240CPWM.
240CPWM requires a six-pulse dynamic DC link voltage that introduces low frequency harmonics in DC input current and/or AC line currents that can affect maximum power point tracking, battery life or THD in line current. Four topologies have been proposed to minimize the low frequency harmonics in input and line currents in grid-connected PV system with 240CPWM.
In order to achieve further benefits in terms of THD and device stress reduction, 240CPWM is extended to three-level inverters. The performance metrics such as THD and switching loss for 240CPWM are analyzed in three-level inverter.
ContributorsQamar, Hafsa (Author) / Ayyanar, Raja (Thesis advisor) / Yu, Hongbin (Committee member) / Lei, Qin (Committee member) / Weng, Yang (Committee member) / Arizona State University (Publisher)
Created2022