ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Barnaby, Hugh
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Space exploration is a large field that requires high performing circuitry due to the harsh environment. Within a space environment one of the biggest factors leading to circuit failure is radiation. Circuits must be robust enough to continue operation after being exposed to the high doses of radiation. Bandgap reference (BGR) circuits are designed to be voltage references that stay stable across a wide range of supply voltages and temperatures. A bandgap reference is a piece of a large circuit that supplies critical elements of the large circuit with a constant voltage. When used in a space environment with large amounts of radiation a BGR needs to maintain its output voltage to enable the rest of the circuit to operate under proper conditions. Since a BGR is not a standalone circuit it is difficult and expensive to test if a BGR is maintaining its reference voltage.
This thesis describes a methodology of isolating and simulating bandgap references. Both NPN and PNP bandgap references are simulated over a variety of radiation doses and dose rates. This methodology will allow the degradation due to radiation of a BGR to be modeled easily and affordably. It can be observed that many circuits experience enhanced low dose rate sensitivity (ELDRS) which can lead to failure at low total ionizing doses (TID) of radiation. A compact model library demonstrating degradation of transistors at both high and low dose rates (HDR and LDR) will be used to show bandgap references reliability. Specifically, two bandgap references being utilized in commercial off the shelf low dropout regulators (LDO) will be evaluated. The LDOs are reverse engineered in a simulation program with integrated circuit emphasis (SPICE). Within the two LDOs the bandgaps will be the points of interest. Of the LDOs one has a positive regulated voltage and one has a negative regulated voltage. This requires an NPN and a PNP based BGR respectively. This simulation methodology will draw conclusions about the above bandgap references, and how they operate under radiation at different doses and dose rates.
This thesis describes a methodology of isolating and simulating bandgap references. Both NPN and PNP bandgap references are simulated over a variety of radiation doses and dose rates. This methodology will allow the degradation due to radiation of a BGR to be modeled easily and affordably. It can be observed that many circuits experience enhanced low dose rate sensitivity (ELDRS) which can lead to failure at low total ionizing doses (TID) of radiation. A compact model library demonstrating degradation of transistors at both high and low dose rates (HDR and LDR) will be used to show bandgap references reliability. Specifically, two bandgap references being utilized in commercial off the shelf low dropout regulators (LDO) will be evaluated. The LDOs are reverse engineered in a simulation program with integrated circuit emphasis (SPICE). Within the two LDOs the bandgaps will be the points of interest. Of the LDOs one has a positive regulated voltage and one has a negative regulated voltage. This requires an NPN and a PNP based BGR respectively. This simulation methodology will draw conclusions about the above bandgap references, and how they operate under radiation at different doses and dose rates.
ContributorsDavis, Parker William (Author) / Barnaby, Hugh (Thesis advisor) / Kitchen, Jennifer (Committee member) / Privat, Aymeric (Committee member) / Arizona State University (Publisher)
Created2019
Description
In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.
ContributorsKim, Kibeom (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2013
Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013