ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Filtering by
- Genre: Doctoral Dissertation
dynamic state estimation problem whose complexity is intensified
under low signal-to-noise ratio (SNR) or high clutter conditions.
This is important, for example, when tracking
multiple, closely spaced targets moving in the same direction such as a
convoy of low observable vehicles moving through a forest or multiple
targets moving in a crisscross pattern. The SNR in
these applications is usually low as the reflected signals from
the targets are weak or the noise level is very high.
An effective approach for detecting and tracking a single target
under low SNR conditions is the track-before-detect filter (TBDF)
that uses unthresholded measurements. However, the TBDF has only been used to
track a small fixed number of targets at low SNR.
This work proposes a new multiple target TBDF approach to track a
dynamically varying number of targets under the recursive Bayesian framework.
For a given maximum number of
targets, the state estimates are obtained by estimating the joint
multiple target posterior probability density function under all possible
target
existence combinations. The estimation of the corresponding target existence
combination probabilities and the target existence probabilities are also
derived. A feasible sequential Monte Carlo (SMC) based implementation
algorithm is proposed. The approximation accuracy of the SMC
method with a reduced number of particles is improved by an efficient
proposal density function that partitions the multiple target space into a
single target space.
The proposed multiple target TBDF method is extended to track targets in sea
clutter using highly time-varying radar measurements. A generalized
likelihood function for closely spaced multiple targets in compound Gaussian
sea clutter is derived together with the maximum likelihood estimate of
the model parameters using an iterative fixed point algorithm.
The TBDF performance is improved by proposing a computationally feasible
method to estimate the space-time covariance matrix of rapidly-varying sea
clutter. The method applies the Kronecker product approximation to the
covariance matrix and uses particle filtering to solve the resulting dynamic
state space model formulation.
Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.
This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks architecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. Each instruction in a SE is locked to a Reservation Station (RS) and revitalizes itself after execution; thus never retiring from the RS. The entire kernel is hosted in RS Banks (RSBs) close to functional units for energy-efficient instruction delivery. The dataflow semantics of stream kernels are captured by a context-aware dataflow execution mode that efficiently exploits the Instruction Level Parallelism (ILP) and Data-level parallelism (DLP) within stream kernels.
Multiple SEs are grouped together to form a StreamCluster (SC) that communicate via a local interconnect. A novel software FIFO virtualization technique with split-join functionality is proposed for efficient and scalable stream communication across SEs. The proposed communication mechanism exploits the Task-level parallelism (TLP) of the stream application. The performance and scalability of the communication mechanism is evaluated against the existing data movement schemes for scratchpad based multi-core architectures. Further, overlay schemes and architectural support are proposed that allow hosting any number of kernels on the StreamWorks architecture. The proposed oevrlay schemes for code management supports kernel(context) switching for the most common use cases and can be adapted for any multi-core architecture that use software managed local memories.
The performance and energy-efficiency of the StreamWorks architecture is evaluated for stream kernel and application benchmarks by implementing the architecture in 45nm TSMC and comparison with a low power RISC core and a contemporary accelerator.