ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- All Subjects: GAN
- Creators: Ayyanar, Raja
Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
Wide-BandGap (WBG) material-based switching devices such as gallium nitride (GaN) High Electron Mobility Transistors (HEMTs) and Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are considered very promising and valuable candidates for replacing conventional Silicon (Si) MOSFETs in various industrial high-frequency high-power applications, mainly because of their capabilities of higher switching frequencies with less switching and conduction losses. However, to make the most of their advantages, it is crucial to understand the intrinsic differences between WBG-based and Si-based switching devices and investigate effective means to safely, efficiently, and reliably utilize the WBG devices. Firstly, a comprehensive understanding of traditional Modular Multilevel Converter (MMC) topology is presented. Different novel SubModule (SM) topologies are described in detail. The low frequency SM voltage fluctuation problem is also discussed. Based on the analysis, some novel topologies which manage to damp or eliminate the voltage ripple are illustrated in detail. As demonstrated, simulation results of these proposed topologies verify the theory. Moreover, the hardware design considerations of traditional MMC platform are discussed. Based on these, a 6 kW smart Modular Isolated Multilevel Converter (MIMC) with symmetrical resonant converter based Ripple current elimination channels is delivered and related experimental results further verify the effectiveness of proposed topology. Secondly, the evolution of GaN transistor structure, from classical normally-on device to normally-off GaN, is well-described. As the benefits, channel current capability and drain-source voltage are significantly boosted. However, accompanying the evolution of GaN devices, the dynamic on-resistance issue is one of the urgent problems to be solved since it strongly affects the GaN device current and voltage limit. Unlike traditional methods from the perspective of transistor structure, this report proposes a novel Multi-Level-Voltage-Output gate drive circuit (MVO-GD) aimed at alleviating the dynamic on-resistance issue from engineering point of view. The comparative tests of proposed MVO-GD and the standard 2-level gate driver (STD-GD) are conducted under variable test conditions which may affect dynamic on-resistance, such as drain-source voltage, gate current width, device package temperature and so on. The experimental waveforms and data have been demonstrated and analyzed.
ContributorsLIU, YIFU (Author) / Lei, Qin (Thesis advisor) / Ayyanar, Raja (Committee member) / Ranjram, Mike (Committee member) / Mallik, Ayan (Committee member) / Arizona State University (Publisher)
Created2022