This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.

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Description
From 2D planar MOSFET to 3D FinFET, the geometry of semiconductor devices is getting more and more complex. Correspondingly, the number of mesh grid points increases largely to maintain the accuracy of carrier transport and heat transfer simulations. By substituting the conventional uniform mesh with non-uniform mesh, one can reduce

From 2D planar MOSFET to 3D FinFET, the geometry of semiconductor devices is getting more and more complex. Correspondingly, the number of mesh grid points increases largely to maintain the accuracy of carrier transport and heat transfer simulations. By substituting the conventional uniform mesh with non-uniform mesh, one can reduce the number of grid points. However, the problem of how to solve governing equations on non-uniform mesh is then imposed to the numerical solver. Moreover, if a device simulator is integrated into a multi-scale simulator, the problem size will be further increased. Consequently, there exist two challenges for the current numerical solver. One is to increase the functionality to accommodate non-uniform mesh. The other is to solve governing physical equations fast and accurately on a large number of mesh grid points.

This research rst discusses a 2D planar MOSFET simulator and its numerical solver, pointing out its performance limit. By analyzing the algorithm complexity, Multigrid method is proposed to replace conventional Successive-Over-Relaxation method in a numerical solver. A variety of Multigrid methods (standard Multigrid, Algebraic Multigrid, Full Approximation Scheme, and Full Multigrid) are discussed and implemented. Their properties are examined through a set of numerical experiments. Finally, Algebraic Multigrid, Full Approximation Scheme and Full Multigrid are integrated into one advanced numerical solver based on the exact requirements of a semiconductor device simulator. A 2D MOSFET device is used to benchmark the performance, showing that the advanced Multigrid method has higher speed, accuracy and robustness.
ContributorsGuo, Xinchen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Ferry, David (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and

Moore's law has been the most important driving force for the tremendous progress of semiconductor industry. With time the transistors which form the fundamental building block of any integrated circuit have been shrinking in size leading to smaller and faster electronic devices.As the devices scale down thermal effects and the short channel effects become the important deciding factors in determining transistor architecture.SOI (Silicon on Insulator) devices have been excellent alternative to planar MOSFET for ultimate CMOS scaling since they mitigate short channel effects. Hence as a part of thesis we tried to study the benefits of the SOI technology especially for lower technology nodes when the channel thickness reduces down to sub 10nm regime. This work tries to explore the effects of structural confinement due to reduced channel thickness on the electrostatic behavior of DG SOI MOSFET. DG SOI MOSFET form the Qfinfet which is an alternative to existing Finfet structure. Qfinfet was proposed and patented by the Finscale Inc for sub 10nm technology nodes.

As part of MS Thesis we developed electrostatic simulator for DG SOI devices by implementing the self consistent full band Schrodinger Poisson solver. We used the Empirical Pseudopotential method in conjunction with supercell approach to solve the Schrodinger Equation. EPM was chosen because it has few empirical parameters which give us good accuracy for experimental results. Also EPM is computationally less expensive as compared to the atomistic methods like DFT(Density functional theory) and NEGF (Non-equilibrium Green's function). In our workwe considered two crystallographic orientations of Si,namely [100] and [110].
ContributorsLaturia, Akash (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2016