ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Mobasher, Barzin
- Creators: Barnaby, Hugh
Description
Static CMOS logic has remained the dominant design style of digital systems for
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
ContributorsYang, Jinghua (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Cao, Yu (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018
Description
The aging mechanism in devices is prone to uncertainties due to dynamic stress conditions. In AMS circuits these can lead to momentary fluctuations in circuit voltage that may be missed by a compact model and hence cause unpredictable failure. Firstly, multiple aging effects in the devices may have underlying correlations. The generation of new traps during TDDB may significantly accelerate BTI, since these traps are close to the dielectric-Si interface in scaled technology. Secondly, the prevalent reliability analysis lacks a direct validation of the lifetime of devices and circuits. The aging mechanism of BTI causes gradual degradation of the device leading to threshold voltage shift and increasing the failure rate. In the 28nm HKMG technology, contribution of BTI to NMOS degradation has become significant at high temperature as compared to Channel Hot Carrier (CHC). This requires revising the End of Lifetime (EOL) calculation based on contribution from induvial aging effects especially in feedback loops. Conventionally, aging in devices is extrapolated from a short-term measurement, but this practice results in unreliable prediction of EOL caused by variability in initial parameters and stress conditions. To mitigate the extrapolation issues and improve predictability, this work aims at providing a new approach to test the device to EOL in a fast and controllable manner. The contributions of this thesis include: (1) based on stochastic trapping/de-trapping mechanism, new compact BTI models are developed and verified with 14nm FinFET and 28nm HKMG data. Moreover, these models are implemented into circuit simulation, illustrating a significant increase in failure rate due to accelerated BTI, (2) developing a model to predict accelerated aging under special conditions like feedback loops and stacked inverters, (3) introducing a feedback loop based test methodology called Adaptive Accelerated Aging (AAA) that can generate accurate aging data till EOL, (4) presenting simulation and experimental data for the models and providing test setup for multiple stress conditions, including those for achieving EOL in 1 hour device as well as ring oscillator (RO) circuit for validation of the proposed methodology, and (5) scaling these models for finding a guard band for VLSI design circuits that can provide realistic aging impact.
ContributorsPatra, Devyani (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Thesis advisor) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2017
Description
VCO as a ubiquitous circuit in many systems is highly demanding for the phase noises. Lowering the noise migrated from the power supply has been the trending topics for many years. Considering the Ring Oscillator(RO) based VCO is more sensitive to the supply noise, it is more significant to find out a useful technique to reduce the supply noise. Among the conventional supply noise reduction techniques such as filtering, channel length adjusting for the transistors, and the current noise mutual canceling, the new feature of the 28nm UTBB-FD-SOI process launched by the ST semiconductor offered a new method to reduce the noise, which is realized by allowing the circuit designer to dynamically control the threshold voltage. In this thesis, a new structure of the linear coarse-fine VCO with 1V supply voltage is designed for the ring typed VCO. The structure is also designed to be flexible to tune the frequency coverage by the fine and coarse tunable on-board resistors. The thesis has given the model of the phase noise reduction method. The model has also been proved to be meaningful with the newly designed VCO circuit. For instances, given 1μV/√Hz white noise coupled on the supply, the 3GHz VCO can have a more than 7dBc/Hz phase noise lowering at the 10MHz frequency offset.
ContributorsTang, Miao (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2018
Description
Concrete is relatively brittle, and its tensile strength is typically only about one-tenth of its compressive strength. Regular concrete is therefore normally uses reinforcement steel bars to increase the tensile strength. It is becoming increasingly popular to use random distributed fibers as reinforcement and polymeric fibers is once such kind. In the case of polymeric fibers, due to hydrophobicity and lack of any chemical bond between the fiber and matrix, the weak interface zone limits the ability of the fibers to effectively carry the load that is on the matrix phase. Depending on the fiber’s surface asperity, shape, chemical nature, and mechanical bond characteristic of the load transfer between matrix and fiber can be altered so that the final composite can be improved. These modifications can be carried out by means of thermal treatment, mechanical surface modifications, or chemical changes The objective of this study is to measure and document the effect of gamma ray irradiation on the mechanical properties of macro polymeric fibers. The objective is to determine the mechanical properties of macro-synthetic fibers and develop guidelines for treatment and characterization that allow for potential positive changes due to exposure to irradiation. Fibers are exposed to various levels of ionizing radiation and the tensile, interface and performance in a mortar matrix are documented. Uniaxial tensile tests were performed on irradiated fibers to study fiber strength and failure pattern. SEM tests were carried out in order to study the surface characteristic and effect of different radiation dose on polymeric fiber. The interaction of the irradiated fiber with the cement composite was studied by a series of quasi-static pullout test for a specific embedded length. As a final task, flexural tests were carried out for different irradiated fibers to sum up the investigation. An average increase of 13% in the stiffness of the fiber was observed for 5 kGy of radiation. Flexural tests showed an average increase of 181% in the Req3 value and 102 % in the toughness of the sample was observed for 5 kGy of dose.
ContributorsTiwari, Sanchay Sushil (Author) / Mobasher, Barzin (Thesis advisor) / Neithalath, Narayanan (Thesis advisor) / Dharmarajan, Subramaniam (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2018
Description
This research summarizes the validation testing completed for the material model MAT213, currently implemented in the LS-DYNA finite element program. Testing was carried out using a carbon fiber composite material, T800-F3900. Stacked-ply tension and compression tests were performed for open-hole and full coupons. Comparisons of experimental and simulation results showed a good agreement between the two for metrics including, stress-strain response and displacements. Strains and displacements in the direction of loading were better predicted by the simulations than for that of the transverse direction.
Double cantilever beam and end notched flexure tests were performed experimentally and through simulations to determine the delamination properties of the material at the interlaminar layers. Experimental results gave the mode I critical energy release rate as having a range of 2.18 – 3.26 psi-in and the mode II critical energy release rate as 10.50 psi-in, both for the pre-cracked condition. Simulations were performed to calibrate other cohesive zone parameters required for modeling.
Samples of tested T800/F3900 coupons were processed and examined with scanning electron microscopy to determine and understand the underlying structure of the material. Tested coupons revealed damage and failure occurring at the micro scale for the composite material.
Double cantilever beam and end notched flexure tests were performed experimentally and through simulations to determine the delamination properties of the material at the interlaminar layers. Experimental results gave the mode I critical energy release rate as having a range of 2.18 – 3.26 psi-in and the mode II critical energy release rate as 10.50 psi-in, both for the pre-cracked condition. Simulations were performed to calibrate other cohesive zone parameters required for modeling.
Samples of tested T800/F3900 coupons were processed and examined with scanning electron microscopy to determine and understand the underlying structure of the material. Tested coupons revealed damage and failure occurring at the micro scale for the composite material.
ContributorsHolt, Nathan T (Author) / Rajan, Subramaniam D. (Thesis advisor) / Mobasher, Barzin (Committee member) / Hoover, Christian (Committee member) / Arizona State University (Publisher)
Created2018
Description
Being a remarkably versatile and inexpensive building material, concrete has found tremendous use in development of modern infrastructure and is the most widely used material in the world. Extensive research in the field of concrete has led to the development of a wide array of concretes with applications ranging from building of skyscrapers to paving of highways. These varied applications require special cementitious composites which can satisfy the demand for enhanced functionalities such as high strength, high durability and improved thermal characteristics among others.
The current study focuses on the fundamental understanding of such functional composites, from their microstructural design to macro-scale application. More specifically, this study investigates three different categories of functional cementitious composites. First, it discusses the differences between cementitious systems containing interground and blended limestone with and without alumina. The interground systems are found to outperform the blended systems due to differential grinding of limestone. A novel approach to deduce the particle size distribution of limestone and cement in the interground systems is proposed. Secondly, the study delves into the realm of ultra-high performance concrete, a novel material which possesses extremely high compressive-, tensile- and flexural-strength and service life as compared to regular concrete. The study presents a novel first principles-based paradigm to design economical ultra-high performance concretes using locally available materials. In the final part, the study addresses the thermal benefits of a novel type of concrete containing phase change materials. A software package was designed to perform numerical simulations to analyze temperature profiles and thermal stresses in concrete structures containing PCMs.
The design of these materials is accompanied by material characterization of cementitious binders. This has been accomplished using techniques that involve measurement of heat evolution (isothermal calorimetry), determination and quantification of reaction products (thermo-gravimetric analysis, x-ray diffraction, micro-indentation, scanning electron microscopy, energy-dispersive x-ray spectroscopy) and evaluation of pore-size distribution (mercury intrusion porosimetry). In addition, macro-scale testing has been carried out to determine compression, flexure and durability response. Numerical simulations have been carried out to understand hydration of cementitious composites, determine optimum particle packing and determine the thermal performance of these composites.
The current study focuses on the fundamental understanding of such functional composites, from their microstructural design to macro-scale application. More specifically, this study investigates three different categories of functional cementitious composites. First, it discusses the differences between cementitious systems containing interground and blended limestone with and without alumina. The interground systems are found to outperform the blended systems due to differential grinding of limestone. A novel approach to deduce the particle size distribution of limestone and cement in the interground systems is proposed. Secondly, the study delves into the realm of ultra-high performance concrete, a novel material which possesses extremely high compressive-, tensile- and flexural-strength and service life as compared to regular concrete. The study presents a novel first principles-based paradigm to design economical ultra-high performance concretes using locally available materials. In the final part, the study addresses the thermal benefits of a novel type of concrete containing phase change materials. A software package was designed to perform numerical simulations to analyze temperature profiles and thermal stresses in concrete structures containing PCMs.
The design of these materials is accompanied by material characterization of cementitious binders. This has been accomplished using techniques that involve measurement of heat evolution (isothermal calorimetry), determination and quantification of reaction products (thermo-gravimetric analysis, x-ray diffraction, micro-indentation, scanning electron microscopy, energy-dispersive x-ray spectroscopy) and evaluation of pore-size distribution (mercury intrusion porosimetry). In addition, macro-scale testing has been carried out to determine compression, flexure and durability response. Numerical simulations have been carried out to understand hydration of cementitious composites, determine optimum particle packing and determine the thermal performance of these composites.
ContributorsArora, Aashay (Author) / Neithalath, Narayanan (Thesis advisor) / Rajan, Subramaniam D. (Committee member) / Mobasher, Barzin (Committee member) / Chawla, Nikhilesh (Committee member) / Hoover, Christian G (Committee member) / Arizona State University (Publisher)
Created2018
Description
Phase change materials (PCMs) are combined sensible-and-latent thermal energy storage materials that can be used to store and dissipate energy in the form of heat. PCMs incorporated into wall-element systems have been well-studied with respect to energy efficiency of building envelopes. New applications of PCMs in infrastructural concrete, e.g., for mitigating early-age cracking and freeze-and-thaw induced damage, have also been proposed. Hence, the focus of this dissertation is to develop a detailed understanding of the physic-chemical and thermo-mechanical characteristics of cementitious systems and novel coating systems for wall-elements containing PCM. The initial phase of this work assesses the influence of interface properties and inter-inclusion interactions between microencapsulated PCM, macroencapsulated PCM, and the cementitious matrix. The fact that these inclusions within the composites are by themselves heterogeneous, and contain multiple components necessitate careful application of models to predict the thermal properties. The next phase observes the influence of PCM inclusions on the fracture and fatigue behavior of PCM-cementitious composites. The compliant nature of the inclusion creates less variability in the fatigue life for these composites subjected to cyclic loading. The incorporation of small amounts of PCM is found to slightly improve the fracture properties compared to PCM free cementitious composites. Inelastic deformations at the crack-tip in the direction of crack opening are influenced by the microscale PCM inclusions. After initial laboratory characterization of the microstructure and evaluation of the thermo-mechanical performance of these systems, field scale applicability and performance were evaluated. Wireless temperature and strain sensors for smart monitoring were embedded within a conventional portland cement concrete pavement (PCCP) and a thermal control smart concrete pavement (TCSCP) containing PCM. The TCSCP exhibited enhanced thermal performance over multiple heating and cooling cycles. PCCP showed significant shrinkage behavior as a result of compressive strains in the reinforcement that were twice that of the TCSCP. For building applications, novel PCM-composites coatings were developed to improve and extend the thermal efficiency. These coatings demonstrated a delay in temperature by up to four hours and were found to be more cost-effective than traditional building insulating materials.
The results of this work prove the feasibility of PCMs as a temperature-regulating technology. Not only do PCMs reduce and control the temperature within cementitious systems without affecting the rate of early property development but they can also be used as an auto-adaptive technology capable of improving the thermal performance of building envelopes.
The results of this work prove the feasibility of PCMs as a temperature-regulating technology. Not only do PCMs reduce and control the temperature within cementitious systems without affecting the rate of early property development but they can also be used as an auto-adaptive technology capable of improving the thermal performance of building envelopes.
ContributorsAguayo, Matthew Joseph (Author) / Neithalath, Narayanan (Thesis advisor) / Rajan, Subramaniam D. (Committee member) / Mobasher, Barzin (Committee member) / Underwood, Benjamin (Committee member) / Liu, Yongming (Committee member) / Arizona State University (Publisher)
Created2018
Description
Semiconductor memory is a key component of the computing systems. Beyond the conventional memory and data storage applications, in this dissertation, both mainstream and eNVM memory technologies are explored for radiation environment, hardware security system and machine learning applications.
In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level.
Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well.
Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm.
Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.
In the radiation environment, e.g. aerospace, the memory devices face different energetic particles. The strike of these energetic particles can generate electron-hole pairs (directly or indirectly) as they pass through the semiconductor device, resulting in photo-induced current, and may change the memory state. First, the trend of radiation effects of the mainstream memory technologies with technology node scaling is reviewed. Then, single event effects of the oxide based resistive switching random memory (RRAM), one of eNVM technologies, is investigated from the circuit-level to the system level.
Physical Unclonable Function (PUF) has been widely investigated as a promising hardware security primitive, which employs the inherent randomness in a physical system (e.g. the intrinsic semiconductor manufacturing variability). In the dissertation, two RRAM-based PUF implementations are proposed for cryptographic key generation (weak PUF) and device authentication (strong PUF), respectively. The performance of the RRAM PUFs are evaluated with experiment and simulation. The impact of non-ideal circuit effects on the performance of the PUFs is also investigated and optimization strategies are proposed to solve the non-ideal effects. Besides, the security resistance against modeling and machine learning attacks is analyzed as well.
Deep neural networks (DNNs) have shown remarkable improvements in various intelligent applications such as image classification, speech classification and object localization and detection. Increasing efforts have been devoted to develop hardware accelerators. In this dissertation, two types of compute-in-memory (CIM) based hardware accelerator designs with SRAM and eNVM technologies are proposed for two binary neural networks, i.e. hybrid BNN (HBNN) and XNOR-BNN, respectively, which are explored for the hardware resource-limited platforms, e.g. edge devices.. These designs feature with high the throughput, scalability, low latency and high energy efficiency. Finally, we have successfully taped-out and validated the proposed designs with SRAM technology in TSMC 65 nm.
Overall, this dissertation paves the paths for memory technologies’ new applications towards the secure and energy-efficient artificial intelligence system.
ContributorsLiu, Rui (Author) / Yu, Shimeng (Thesis advisor, Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018
Description
The rapid improvement in computation capability has made deep convolutional neural networks (CNNs) a great success in recent years on many computer vision tasks with significantly improved accuracy. During the inference phase, many applications demand low latency processing of one image with strict power consumption requirement, which reduces the efficiency of GPU and other general-purpose platform, bringing opportunities for specific acceleration hardware, e.g. FPGA, by customizing the digital circuit specific for the deep learning algorithm inference. However, deploying CNNs on portable and embedded systems is still challenging due to large data volume, intensive computation, varying algorithm structures, and frequent memory accesses. This dissertation proposes a complete design methodology and framework to accelerate the inference process of various CNN algorithms on FPGA hardware with high performance, efficiency and flexibility.
As convolution contributes most operations in CNNs, the convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN accelerator. Convolution involves multiply and accumulate (MAC) operations with four levels of loops. Without fully studying the convolution loop optimization before the hardware design phase, the resulting accelerator can hardly exploit the data reuse and manage data movement efficiently. This work overcomes these barriers by quantitatively analyzing and optimizing the design objectives (e.g. memory access) of the CNN accelerator based on multiple design variables. An efficient dataflow and hardware architecture of CNN acceleration are proposed to minimize the data communication while maximizing the resource utilization to achieve high performance.
Although great performance and efficiency can be achieved by customizing the FPGA hardware for each CNN model, significant efforts and expertise are required leading to long development time, which makes it difficult to catch up with the rapid development of CNN algorithms. In this work, we present an RTL-level CNN compiler that automatically generates customized FPGA hardware for the inference tasks of various CNNs, in order to enable high-level fast prototyping of CNNs from software to FPGA and still keep the benefits of low-level hardware optimization. First, a general-purpose library of RTL modules is developed to model different operations at each layer. The integration and dataflow of physical modules are predefined in the top-level system template and reconfigured during compilation for a given CNN algorithm. The runtime control of layer-by-layer sequential computation is managed by the proposed execution schedule so that even highly irregular and complex network topology, e.g. GoogLeNet and ResNet, can be compiled. The proposed methodology is demonstrated with various CNN algorithms, e.g. NiN, VGG, GoogLeNet and ResNet, on two different standalone FPGAs achieving state-of-the art performance.
Based on the optimized acceleration strategy, there are still a lot of design options, e.g. the degree and dimension of computation parallelism, the size of on-chip buffers, and the external memory bandwidth, which impact the utilization of computation resources and data communication efficiency, and finally affect the performance and energy consumption of the accelerator. The large design space of the accelerator makes it impractical to explore the optimal design choice during the real implementation phase. Therefore, a performance model is proposed in this work to quantitatively estimate the accelerator performance and resource utilization. By this means, the performance bottleneck and design bound can be identified and the optimal design option can be explored early in the design phase.
As convolution contributes most operations in CNNs, the convolution acceleration scheme significantly affects the efficiency and performance of a hardware CNN accelerator. Convolution involves multiply and accumulate (MAC) operations with four levels of loops. Without fully studying the convolution loop optimization before the hardware design phase, the resulting accelerator can hardly exploit the data reuse and manage data movement efficiently. This work overcomes these barriers by quantitatively analyzing and optimizing the design objectives (e.g. memory access) of the CNN accelerator based on multiple design variables. An efficient dataflow and hardware architecture of CNN acceleration are proposed to minimize the data communication while maximizing the resource utilization to achieve high performance.
Although great performance and efficiency can be achieved by customizing the FPGA hardware for each CNN model, significant efforts and expertise are required leading to long development time, which makes it difficult to catch up with the rapid development of CNN algorithms. In this work, we present an RTL-level CNN compiler that automatically generates customized FPGA hardware for the inference tasks of various CNNs, in order to enable high-level fast prototyping of CNNs from software to FPGA and still keep the benefits of low-level hardware optimization. First, a general-purpose library of RTL modules is developed to model different operations at each layer. The integration and dataflow of physical modules are predefined in the top-level system template and reconfigured during compilation for a given CNN algorithm. The runtime control of layer-by-layer sequential computation is managed by the proposed execution schedule so that even highly irregular and complex network topology, e.g. GoogLeNet and ResNet, can be compiled. The proposed methodology is demonstrated with various CNN algorithms, e.g. NiN, VGG, GoogLeNet and ResNet, on two different standalone FPGAs achieving state-of-the art performance.
Based on the optimized acceleration strategy, there are still a lot of design options, e.g. the degree and dimension of computation parallelism, the size of on-chip buffers, and the external memory bandwidth, which impact the utilization of computation resources and data communication efficiency, and finally affect the performance and energy consumption of the accelerator. The large design space of the accelerator makes it impractical to explore the optimal design choice during the real implementation phase. Therefore, a performance model is proposed in this work to quantitatively estimate the accelerator performance and resource utilization. By this means, the performance bottleneck and design bound can be identified and the optimal design option can be explored early in the design phase.
ContributorsMa, Yufei (Author) / Vrudhula, Sarma (Thesis advisor) / Seo, Jae-Sun (Thesis advisor) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2018
Description
Space exploration is a large field that requires high performing circuitry due to the harsh environment. Within a space environment one of the biggest factors leading to circuit failure is radiation. Circuits must be robust enough to continue operation after being exposed to the high doses of radiation. Bandgap reference (BGR) circuits are designed to be voltage references that stay stable across a wide range of supply voltages and temperatures. A bandgap reference is a piece of a large circuit that supplies critical elements of the large circuit with a constant voltage. When used in a space environment with large amounts of radiation a BGR needs to maintain its output voltage to enable the rest of the circuit to operate under proper conditions. Since a BGR is not a standalone circuit it is difficult and expensive to test if a BGR is maintaining its reference voltage.
This thesis describes a methodology of isolating and simulating bandgap references. Both NPN and PNP bandgap references are simulated over a variety of radiation doses and dose rates. This methodology will allow the degradation due to radiation of a BGR to be modeled easily and affordably. It can be observed that many circuits experience enhanced low dose rate sensitivity (ELDRS) which can lead to failure at low total ionizing doses (TID) of radiation. A compact model library demonstrating degradation of transistors at both high and low dose rates (HDR and LDR) will be used to show bandgap references reliability. Specifically, two bandgap references being utilized in commercial off the shelf low dropout regulators (LDO) will be evaluated. The LDOs are reverse engineered in a simulation program with integrated circuit emphasis (SPICE). Within the two LDOs the bandgaps will be the points of interest. Of the LDOs one has a positive regulated voltage and one has a negative regulated voltage. This requires an NPN and a PNP based BGR respectively. This simulation methodology will draw conclusions about the above bandgap references, and how they operate under radiation at different doses and dose rates.
This thesis describes a methodology of isolating and simulating bandgap references. Both NPN and PNP bandgap references are simulated over a variety of radiation doses and dose rates. This methodology will allow the degradation due to radiation of a BGR to be modeled easily and affordably. It can be observed that many circuits experience enhanced low dose rate sensitivity (ELDRS) which can lead to failure at low total ionizing doses (TID) of radiation. A compact model library demonstrating degradation of transistors at both high and low dose rates (HDR and LDR) will be used to show bandgap references reliability. Specifically, two bandgap references being utilized in commercial off the shelf low dropout regulators (LDO) will be evaluated. The LDOs are reverse engineered in a simulation program with integrated circuit emphasis (SPICE). Within the two LDOs the bandgaps will be the points of interest. Of the LDOs one has a positive regulated voltage and one has a negative regulated voltage. This requires an NPN and a PNP based BGR respectively. This simulation methodology will draw conclusions about the above bandgap references, and how they operate under radiation at different doses and dose rates.
ContributorsDavis, Parker William (Author) / Barnaby, Hugh (Thesis advisor) / Kitchen, Jennifer (Committee member) / Privat, Aymeric (Committee member) / Arizona State University (Publisher)
Created2019