ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Kaloush, Kamil
- Creators: Barnaby, Hugh
Description
In recent years, an increase of environmental temperature in urban areas has raised many concerns. These areas are subjected to higher temperature compared to the rural surrounding areas. Modification of land surface and the use of materials such as concrete and/or asphalt are the main factors influencing the surface energy balance and therefore the environmental temperature in the urban areas. Engineered materials have relatively higher solar energy absorption and tend to trap a relatively higher incoming solar radiation. They also possess a higher heat storage capacity that allows them to retain heat during the day and then slowly release it back into the atmosphere as the sun goes down. This phenomenon is known as the Urban Heat Island (UHI) effect and causes an increase in the urban air temperature. Many researchers believe that albedo is the key pavement affecting the urban heat island. However, this research has shown that the problem is more complex and that solar reflectivity may not be the only important factor to evaluate the ability of a pavement to mitigate UHI. The main objective of this study was to analyze and research the influence of pavement materials on the near surface air temperature. In order to accomplish this effort, test sections consisting of Hot Mix Asphalt (HMA), Porous Hot Mix asphalt (PHMA), Portland Cement Concrete (PCC), Pervious Portland Cement Concrete (PPCC), artificial turf, and landscape gravels were constructed in the Phoenix, Arizona area. Air temperature, albedo, wind speed, solar radiation, and wind direction were recorded, analyzed and compared above each pavement material type. The results showed that there was no significant difference in the air temperature at 3-feet and above, regardless of the type of the pavement. Near surface pavement temperatures were also measured and modeled. The results indicated that for the UHI analysis, it is important to consider the interaction between pavement structure, material properties, and environmental factors. Overall, this study demonstrated the complexity of evaluating pavement structures for UHI mitigation; it provided great insight on the effects of material types and properties on surface temperatures and near surface air temperature.
ContributorsPourshams-Manzouri, Tina (Author) / Kaloush, Kamil (Thesis advisor) / Wang, Zhihua (Thesis advisor) / Zapata, Claudia E. (Committee member) / Mamlouk, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Vehicle type choice is a significant determinant of fuel consumption and energy sustainability; larger, heavier vehicles consume more fuel, and expel twice as many pollutants, than their smaller, lighter counterparts. Over the course of the past few decades, vehicle type choice has seen a vast shift, due to many households making more trips in larger vehicles with lower fuel economy. During the 1990s, SUVs were the fastest growing segment of the automotive industry, comprising 7% of the total light vehicle market in 1990, and 25% in 2005. More recently, due to rising oil prices, greater awareness to environmental sensitivity, the desire to reduce dependence on foreign oil, and the availability of new vehicle technologies, many households are considering the use of newer vehicles with better fuel economy, such as hybrids and electric vehicles, over the use of the SUV or low fuel economy vehicles they may already own. The goal of this research is to examine how vehicle miles traveled, fuel consumption and emissions may be reduced through shifts in vehicle type choice behavior. Using the 2009 National Household Travel Survey data it is possible to develop a model to estimate household travel demand and total fuel consumption. If given a vehicle choice shift scenario, using the model it would be possible to calculate the potential fuel consumption savings that would result from such a shift. In this way, it is possible to estimate fuel consumption reductions that would take place under a wide variety of scenarios.
ContributorsChristian, Keith (Author) / Pendyala, Ram M. (Thesis advisor) / Chester, Mikhail (Committee member) / Kaloush, Kamil (Committee member) / Ahn, Soyoung (Committee member) / Arizona State University (Publisher)
Created2013
Description
ABSTRACT Developing new non-traditional device models is gaining popularity as the silicon-based electrical device approaches its limitation when it scales down. Membrane systems, also called P systems, are a new class of biological computation model inspired by the way cells process chemical signals. Spiking Neural P systems (SNP systems), a certain kind of membrane systems, is inspired by the way the neurons in brain interact using electrical spikes. Compared to the traditional Boolean logic, SNP systems not only perform similar functions but also provide a more promising solution for reliable computation. Two basic neuron types, Low Pass (LP) neurons and High Pass (HP) neurons, are introduced. These two basic types of neurons are capable to build an arbitrary SNP neuron. This leads to the conclusion that these two basic neuron types are Turing complete since SNP systems has been proved Turing complete. These two basic types of neurons are further used as the elements to construct general-purpose arithmetic circuits, such as adder, subtractor and comparator. In this thesis, erroneous behaviors of neurons are discussed. Transmission error (spike loss) is proved to be equivalent to threshold error, which makes threshold error discussion more universal. To improve the reliability, a new structure called motif is proposed. Compared to Triple Modular Redundancy improvement, motif design presents its efficiency and effectiveness in both single neuron and arithmetic circuit analysis. DRAM-based CMOS circuits are used to implement the two basic types of neurons. Functionality of basic type neurons is proved using the SPICE simulations. The motif improved adder and the comparator, as compared to conventional Boolean logic design, are much more reliable with lower leakage, and smaller silicon area. This leads to the conclusion that SNP system could provide a more promising solution for reliable computation than the conventional Boolean logic.
ContributorsAn, Pei (Author) / Cao, Yu (Thesis advisor) / Barnaby, Hugh (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2013
Description
Heating of asphalt during production and construction causes the volatilization and oxidation of binders used in mixes. Volatilization and oxidation causes degradation of asphalt pavements by increasing the stiffness of the binders, increasing susceptibility to cracking and negatively affecting the functional and structural performance of the pavements. Degradation of asphalt binders by volatilization and oxidation due to high production temperature occur during early stages of pavement life and are known as Short Term Aging (STA). Elevated temperatures and increased exposure time to elevated temperatures causes increased STA of asphalt. The objective of this research was to investigate how elevated mixing temperatures and exposure time to elevated temperatures affect aging and stiffening of binders, thus influencing properties of the asphalt mixtures. The study was conducted in two stages. The first stage evaluated STA effect of asphalt binders. It involved aging two Performance Graded (PG) virgin asphalt binders, PG 76-16 and PG 64-22 at two different temperatures and durations, then measuring their viscosities. The second stage involved evaluating the effects of elevated STA temperature and time on properties of the asphalt mixtures. It involved STA of asphalt mixtures produced in the laboratory with the PG 64-22 binder at mixing temperatures elevated 25OF above standard practice; STA times at 2 and 4 hours longer than standard practices, and then compacted in a gyratory compactor. Dynamic modulus (E*) and Indirect Tensile Strength (IDT) were measured for the aged mixtures for each temperature and duration to determine the effect of different aging times and temperatures on the stiffness and fatigue properties of the aged asphalt mixtures. The binder test results showed that in all cases, there was increased viscosity. The results showed the highest increase in viscosity resulted from increased aging time. The results also indicated that PG 64-22 was more susceptible to elevated STA temperature and extended time than the PG 76-16 binders. The asphalt mixture test results confirmed the expected outcome that increasing the STA and mixing temperature by 25oF alters the stiffness of mixtures. Significant change in the dynamic modulus mostly occurred at four hour increase in STA time regardless of temperature.
ContributorsLolly, Rubben (Author) / Kaloush, Kamil (Thesis advisor) / Bearup, Wylie (Committee member) / Zapata, Claudia (Committee member) / Mamlouk, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Laboratory assessment of crack resistance and propagation in asphalt concrete is a difficult task that challenges researchers and engineers. Several fracture mechanics based laboratory tests currently exist; however, these tests and subsequent analysis methods rely on elastic behavior assumptions and do not consider the time-dependent nature of asphalt concrete. The C* Line Integral test has shown promise to capture crack resistance and propagation within asphalt concrete. In addition, the fracture mechanics based C* parameter considers the time-dependent creep behavior of the materials. However, previous research was limited and lacked standardized test procedure and detailed data analysis methods were not fully presented. This dissertation describes the development and refinement of the C* Fracture Test (CFT) based on concepts of the C* line integral test. The CFT is a promising test to assess crack propagation and fracture resistance especially in modified mixtures. A detailed CFT test protocol was developed based on a laboratory study of different specimen sizes and test conditions. CFT numerical simulations agreed with laboratory results and indicated that the maximum horizontal tensile stress (Mode I) occurs at the crack tip but diminishes at longer crack lengths when shear stress (Mode II) becomes present. Using CFT test results and the principles of time-temperature superposition, a crack growth rate master curve was successfully developed to describe crack growth over a range of test temperatures. This master curve can be applied to pavement design and analysis to describe crack propagation as a function of traffic conditions and pavement temperatures. Several plant mixtures were subjected to the CFT and results showed differences in resistance to crack propagation, especially when comparing an asphalt rubber mixture to a conventional one. Results indicated that crack propagation is ideally captured within a given range of dynamic modulus values. Crack growth rates and C* prediction models were successfully developed for all unmodified mixtures in the CFT database. These models can be used to predict creep crack propagation and the C* parameter when laboratory testing is not feasible. Finally, a conceptual approach to incorporate crack growth rate and the C* parameter into pavement design and analysis was presented.
ContributorsStempihar, Jeffrey (Author) / Kaloush, Kamil (Thesis advisor) / Witczak, Matthew (Committee member) / Mamlouk, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
The dissolution of metal layers such as silver into chalcogenide glass layers such as germanium selenide changes the resistivity of the metal and chalcogenide films by a great extent. It is known that the incorporation of the metal can be achieved by ultra violet light exposure or thermal processes. In this work, the use of metal dissolution by exposure to gamma radiation has been explored for radiation sensor applications. Test structures were designed and a process flow was developed for prototype sensor fabrication. The test structures were designed such that sensitivity to radiation could be studied. The focus is on the effect of gamma rays as well as ultra violet light on silver dissolution in germanium selenide (Ge30Se70) chalcogenide glass. Ultra violet radiation testing was used prior to gamma exposure to assess the basic mechanism. The test structures were electrically characterized prior to and post irradiation to assess resistance change due to metal dissolution. A change in resistance was observed post irradiation and was found to be dependent on the radiation dose. The structures were also characterized using atomic force microscopy and roughness measurements were made prior to and post irradiation. A change in roughness of the silver films on Ge30Se70 was observed following exposure. This indicated the loss of continuity of the film which causes the increase in silver film resistance following irradiation. Recovery of initial resistance in the structures was also observed after the radiation stress was removed. This recovery was explained with photo-stimulated deposition of silver from the chalcogenide at room temperature confirmed with the re-appearance of silver dendrites on the chalcogenide surface. The results demonstrate that it is possible to use the metal dissolution effect in radiation sensing applications.
ContributorsChandran, Ankitha (Author) / Kozicki, Michael N (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. This metric is useful, but incomplete in that it ignores Sensitivity level, bit error rate, and immunity to interferers. In this study exploration of receiver architectures and convergence upon a comprehensive solution is done. This analysis is used to design and build a system for validation. The Direct Conversion Receiver architecture implemented for the MICS standard in 0.18 µm CMOS process consumes approximately 2 mW is competitive with published research.
ContributorsStevens, Mark (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
The advent of threshold logic simplifies the traditional Boolean logic to the single level multi-input function. Threshold logic latch (TLL), among implementations of threshold logic, is functionally equivalent to a multi-input function with an edge triggered flip-flop, which stands out to improve area and both dynamic and leakage power consumption, providing an appropriate design alternative. Accordingly, the TLL standard cell library is designed. Through technology mapping, hybrid circuit is generated by absorbing the logic cone backward from each flip-flip to get the smallest remaining feeder. With the scan test methodology adopted, design for testability (DFT) is proposed, including scan element design and scan chain insertion. Test synthesis flow is then introduced, according to the Cadence tool, RTL compiler. Test application is the process of applying vectors and the response analysis, which is mainly about the testbench design. A parameterized generic self-checking Verilog testbench is designed for static fault detection. Test development refers to the fault modeling, and test generation. Firstly, functional truth table test generation on TLL cells is proposed. Before the truth table test of the threshold function, the dependence of sequence of vectors applied, i.e., the dependence of current state on the previous state, should be eliminated. Transition test (dynamic pattern) on all weak inputs is proved to be able to test the reset function, which is supposed to erase the history in the reset phase before every evaluation phase. Remaining vectors in the truth table except the weak inputs are then applied statically (static pattern). Secondly, dynamic patterns for all weak inputs are proposed to detect structural transistor level faults analyzed in the TLL cell, with single fault assumption and stuck-at faults, stuck-on faults, and stuck-open faults under consideration. Containing those patterns, the functional test covers all testable structural faults inside the TLL. Thirdly, with the scope of the whole hybrid netlist, the procedure of test generation is proposed with three steps: scan chain test; test of feeders and other scan elements except TLLs; functional pattern test of TLL cells. Implementation of this procedure is discussed in the automatic test pattern generation (ATPG) chapter.
ContributorsHu, Yang (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2013