ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Bakkaloglu, Bertan
- Creators: Herrmann, Marcus
Description
With the increasing focus on developing environmentally benign electronic packages, lead-free solder alloys have received a great deal of attention. Mishandling of packages, during manufacture, assembly, or by the user may cause failure of solder joint. A fundamental understanding of the behavior of lead-free solders under mechanical shock conditions is lacking. Reliable experimental and numerical analysis of lead-free solder joints in the intermediate strain rate regime need to be investigated. This dissertation mainly focuses on exploring the mechanical shock behavior of lead-free tin-rich solder alloys via multiscale modeling and numerical simulations. First, the macroscopic stress/strain behaviors of three bulk lead-free tin-rich solders were tested over a range of strain rates from 0.001/s to 30/s. Finite element analysis was conducted to determine appropriate specimen geometry that could reach a homogeneous stress/strain field and a relatively high strain rate. A novel self-consistent true stress correction method is developed to compensate the inaccuracy caused by the triaxial stress state at the post-necking stage. Then the material property of micron-scale intermetallic was examined by micro-compression test. The accuracy of this measure is systematically validated by finite element analysis, and empirical adjustments are provided. Moreover, the interfacial property of the solder/intermetallic interface is investigated, and a continuum traction-separation law of this interface is developed from an atomistic-based cohesive element method. The macroscopic stress/strain relation and microstructural properties are combined together to form a multiscale material behavior via a stochastic approach for both solder and intermetallic. As a result, solder is modeled by porous plasticity with random voids, and intermetallic is characterized as brittle material with random vulnerable region. Thereafter, the porous plasticity fracture of the solders and the brittle fracture of the intermetallics are coupled together in one finite element model. Finally, this study yields a multiscale model to understand and predict the mechanical shock behavior of lead-free tin-rich solder joints. Different fracture patterns are observed for various strain rates and/or intermetallic thicknesses. The predictions have a good agreement with the theory and experiments.
ContributorsFei, Huiyang (Author) / Jiang, Hanqing (Thesis advisor) / Chawla, Nikhilesh (Thesis advisor) / Tasooji, Amaneh (Committee member) / Mobasher, Barzin (Committee member) / Rajan, Subramaniam D. (Committee member) / Arizona State University (Publisher)
Created2011
Description
The Magnetoplasmadynamic (MPD) thruster is an electromagnetic thruster that produces a higher specific impulse than conventional chemical rockets and greater thrust densities than electrostatic thrusters, but the well-known operational limit---referred to as ``onset"---imposes a severe limitation efficiency and lifetime. This phenomenon is associated with large fluctuations in operating voltage, high rates of electrode erosion, and three-dimensional instabilities in the plasma flow-field which cannot be adequately represented by two-dimensional, axisymmetric models. Simulations of the Princeton Benchmark Thruster (PBT) were conducted using the three-dimensional version of the magnetohydrodynamic (MHD) code, MACH. Validation of the numerical model is partially achieved by comparison to equivalent simulations conducted using the well-established two-dimensional, axisymmetric version of MACH. Comparisons with available experimental data was subsequently performed to further validate the model and gain insights into the physical processes of MPD acceleration. Thrust, plasma voltage, and plasma flow-field predictions were calculated for the PBT operating with applied currents in the range $6.5kA < J < 23.25kA$ and mass-flow rates of $1g/s$, $3g/s$, and $6g/s$. Comparisons of performance characteristics between the two versions of the code show excellent agreement, indicating that MACH3 can be expected to be as predictive as MACH2 has demonstrated over multiple applications to MPD thrusters. Predicted thrust for operating conditions within the range which exhibited no symptoms of the onset phenomenon experimentally also showed agreement between MACH3 and experiment well within the experimental uncertainty. At operating conditions beyond such values , however, there is a discrepancy---up to $\sim20\%$---which implies that certain significant physical processes associated with onset are not currently being modeled. Such processes are also evident in the experimental total voltage data, as is evident by the characteristic ``voltage hash", but not present in predicted plasma voltage. Additionally, analysis of the predicted plasma flow-field shows no breakdown in azimuthal symmetry, which is expected to be associated with onset. This implies that perhaps certain physical processes are modeled by neither MACH2 nor MACH3; the latter indicating that such phenomenon may not be inherently three dimensional and related to the plasma---as suggested by other efforts---but rather a consequence of electrode material processes which have not been incorporated into the current models.
ContributorsParma, Brian (Author) / Mikellides, Pavlos G (Thesis advisor) / Squires, Kyle (Committee member) / Herrmann, Marcus (Committee member) / Arizona State University (Publisher)
Created2011
Description
Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
One of the challenges in future semiconductor device design is excessive rise of power dissipation and device temperatures. With the introduction of new geometrically confined device structures like SOI, FinFET, nanowires and continuous incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. This work examines the degradation in the ON-current due to self-heating effects in 10 nm channel length silicon nanowire transistors. As part of this dissertation, a 3D electrothermal device simulator is developed that self-consistently solves electron Boltzmann transport equation with 3D energy balance equations for both the acoustic and the optical phonons. This device simulator predicts temperature variations and other physical and electrical parameters across the device for different bias and boundary conditions. The simulation results show insignificant current degradation for nanowire self-heating because of pronounced velocity overshoot effect. In addition, this work explores the role of various placement of the source and drain contacts on the magnitude of self-heating effect in nanowire transistors. This work also investigates the simultaneous influence of self-heating and random charge effects on the magnitude of the ON current for both positively and negatively charged single charges. This research suggests that the self-heating effects affect the ON-current in two ways: (1) by lowering the barrier at the source end of the channel, thus allowing more carriers to go through, and (2) via the screening effect of the Coulomb potential. To examine the effect of temperature dependent thermal conductivity of thin silicon films in nanowire transistors, Selberherr's thermal conductivity model is used in the device simulator. The simulations results show larger current degradation because of self-heating due to decreased thermal conductivity . Crystallographic direction dependent thermal conductivity is also included in the device simulations. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction which is in agreement with the values for the thermal conductivity tensor provided by Zlatan Aksamija.
ContributorsHossain, Arif (Author) / Vasileska, Dragica (Thesis advisor) / Ahmed, Shaikh (Committee member) / Bakkaloglu, Bertan (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2011
Description
A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA
ContributorsNaqvi, Syed Roomi (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chae, Junseok (Committee member) / Barnby, Hugh (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2011
Description
Microchannel heat sinks can possess heat transfer characteristics unavailable in conventional heat exchangers; such sinks offer compact solutions to otherwise intractable thermal management problems, notably in small-scale electronics cooling. Flow boiling in microchannels allows a very high heat transfer rate, but is bounded by the critical heat flux (CHF). This thesis presents a theoretical-numerical study of a method to improve the heat rejection capability of a microchannel heat sink via expansion of the channel cross-section along the flow direction. The thermodynamic quality of the refrigerant increases during flow boiling, decreasing the density of the bulk coolant as it flows. This may effect pressure fluctuations in the channels, leading to nonuniform heat transfer and local dryout in regions exceeding CHF. This undesirable phenomenon is counteracted by permitting the cross-section of the microchannel to increase along the direction of flow, allowing more volume for the vapor. Governing equations are derived from a control-volume analysis of a single heated rectangular microchannel; the cross-section is allowed to expand in width and height. The resulting differential equations are solved numerically for a variety of channel expansion profiles and numbers of channels. The refrigerant is R-134a and channel parameters are based on a physical test bed in a related experiment. Significant improvement in CHF is possible with moderate area expansion. Minimal additional manufacturing costs could yield major gains in the utility of microchannel heat sinks. An optimum expansion rate occurred in certain cases, and alterations in the channel width are, in general, more effective at improving CHF than alterations in the channel height. Modest expansion in height enables small width expansions to be very effective.
ContributorsMiner, Mark (Author) / Phelan, Patrick E (Thesis advisor) / Herrmann, Marcus (Committee member) / Chen, Kangping (Committee member) / Arizona State University (Publisher)
Created2011
Description
Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The critical aspect in the application of RNS is the selection of the moduli set and the design of the conversion units. There have been several RNS moduli sets proposed for the implementation of digital filters. However, some are unbalanced and some do not provide the required dynamic range. This thesis addresses the drawbacks of existing RNS moduli sets and proposes a new moduli set for efficient implementation of FIR filters. An efficient VLSI implementation model has been derived for the design of a reverse converter from RNS to the conventional two's complement representation. This model facilitates the realization of a reverse converter for better performance with less hardware complexity when compared with the reverse converter designs of the existing balanced 4-moduli sets. Experimental results comparing multiply and accumulate units using RNS that are implemented using the proposed four-moduli set with the state-of-the-art balanced four-moduli sets, show large improvements in area (46%) and power (43%) reduction for various dynamic ranges. RNS FIR filters using the proposed moduli-set and existing balanced 4-moduli set are implemented in RTL and compared for chip area and power and observed 20% improvements. This thesis also presents threshold logic implementation of the reverse converter.
ContributorsChalivendra, Gayathri (Author) / Vrudhula, Sarma (Thesis advisor) / Shrivastava, Aviral (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Thin film transistors (TFTs) are being used in a wide variety of applications such as image sensors, radiation detectors, as well as for use in liquid crystal displays. However, there is a conspicuous absence of interface electronics for bridging the gap between the flexible sensors and digitized displays. Hence is the need to build the same. In this thesis, the feasibility of building mixed analog circuits in TFTs are explored and demonstrated. A flexible CMOS op-amp is demonstrated using a-Si:H and pentacene TFTs. The achieved performance is ¡Ö 50 dB of DC open loop gain with unity gain frequency (UGF) of 7 kHz. The op-amp is built on the popular 2 stage topology with the 2nd stage being cascoded to provide sufficient gain. A novel biasing circuit was successfully developed modifying the gm biasing circuit to retard the performance degradation as the TFTs aged. A switched capacitor 7 bit DAC was developed in only nMOS topology using a-Si:H TFTs, based on charge sharing concept. The DAC achieved a maximum differential non-linearity (DNL) of 0.6 least significant bit (LSB), while the maximum integral non-linearity (INL) was 1 LSB. TFTs were used as switches in this architecture; as a result the performance was quite unchanged even as the TFTs degraded. A 5 bit fully flash ADC was also designed using all nMOS a-Si:H TFTs. Gray coding was implemented at the output to avoid errors due to comparator meta-stability. Finally a 5 bit current steering DAC was also built using all nMOS a-Si:H TFTs. However, due to process variation, the DNL was increased to 1.2 while the INL was about 1.8 LSB. Measurements were made on the external stress effects on zinc indium oxide (ZIO) TFTs. Electrically induced stresses were studied applying DC bias on the gate and drain. These stresses shifted the device characteristics like threshold voltage and mobility. The TFTs were then mechanically stressed by stretching them across cylindrical structures of various radii. Both the subthreshold swing and mobility underwent significant changes when the stress was tensile while the change was minor under compressive stress, applied parallel to channel length.
ContributorsDey, Aritra (Author) / Allee, David R. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Garrity, Douglas A (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence T (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral analysis of output from the BiST circuitry using an analytical method. Matlab was used to simulate the system with known test impairments and impairment values from simulations were calculated based on system modeling in Mathematica. Simulated data is in good correlation with input test data along with very fast test time and high accuracy. The key contribution of the work is that, system impairments are extracted from transmitter response at baseband frequency using envelope detector hence eliminating the need of expensive high frequency ATE (Automated Test Equipments).
ContributorsGoyal, Nitin (Author) / Ozev, Sule (Thesis advisor) / Duman, Tolga (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011