ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Alford, Terry
- Creators: Shrivastava, Aviral
Description
The overall goal of this research project was to assess the feasibility of investigating the effects of microgravity on mineralization systems in unit gravity environments. If possible to perform these studies in unit gravity earth environments, such as earth, such systems can offer markedly less costly and more concerted research efforts to study these vitally important systems. Expected outcomes from easily accessible test environments and more tractable studies include the development of more advanced and adaptive material systems, including biological systems, particularly as humans ponder human exploration in deep space. The specific focus of the research was the design and development of a prototypical experimental test system that could preliminarily meet the challenging design specifications required of such test systems. Guided by a more unified theoretical foundation and building upon concept design and development heuristics, assessment of the feasibility of two experimental test systems was explored. Test System I was a rotating wall reactor experimental system that closely followed the specifications of a similar test system, Synthecon, designed by NASA contractors and thus closely mimicked microgravity conditions of the space shuttle and station. The latter includes terminal velocity conditions experienced by both innate material systems, as well as, biological systems, including living tissue and humans but has the ability to extend to include those material test systems associated with mineralization processes. Test System II is comprised of a unique vertical column design that offered more easily controlled fluid mechanical test conditions over a much wider flow regime that was necessary to achieving terminal velocities under free convection-less conditions that are important in mineralization processes. Preliminary results indicate that Test System II offers distinct advantages in studying microgravity effects in test systems operating in unit gravity environments and particularly when investigating mineralization and related processes. Verification of the Test System II was performed on validating microgravity effects on calcite mineralization processes reported earlier others. There studies were conducted on calcite mineralization in fixed-wing, reduced gravity aircraft, known as the `vomit comet' where reduced gravity conditions are include for very short (~20second) time periods. Preliminary results indicate that test systems, such as test system II, can be devised to assess microgravity conditions in unit gravity environments, such as earth. Furthermore, the preliminary data obtained on calcite formation suggest that strictly physicochemical mechanisms may be the dominant factors that control adaptation in materials processes, a theory first proposed by Liu et al. Thus the result of this study may also help shine a light on the problem of early osteoporosis in astronauts and long term interest in deep space exploration.
ContributorsSeyedmadani, Kimia (Author) / Pizziconi, Vincent (Thesis advisor) / Towe, Bruce (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2013
Description
As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. The focus of this work is to understand the properties of charges present in the SiNx films and then to develop a mechanism to manipulate the polarity of charges to either negative or positive based on the end-application. Specific silicon-nitrogen dangling bonds (·Si-N), known as K center defects, are the primary charge trapping defects present in the SiNx films. A custom built corona charging tool was used to externally inject positive or negative charges in the SiNx film. Detailed Capacitance-Voltage (C-V) measurements taken on corona charged SiNx samples confirmed the presence of a net positive or negative charge density, as high as +/- 8 x 1012 cm-2, present in the SiNx film. High-energy (~ 4.9 eV) UV radiation was used to control and neutralize the charges in the SiNx films. Electron-Spin-Resonance (ESR) technique was used to detect and quantify the density of neutral K0 defects that are paramagnetically active. The density of the neutral K0 defects increased after UV treatment and decreased after high temperature annealing and charging treatments. Etch-back C-V measurements on SiNx films showed that the K centers are spread throughout the bulk of the SiNx film and not just near the SiNx-Si interface. It was also shown that the negative injected charges in the SiNx film were stable and present even after 1 year under indoor room-temperature conditions. Lastly, a stack of SiO2/SiNx dielectric layers applicable to standard commercial solar cells was developed using a low temperature (< 400 °C) PECVD process. Excellent surface passivation on FZ and CZ Si substrates for both n- and p-type samples was achieved by manipulating and controlling the charge in SiNx films.
ContributorsSharma, Vivek (Author) / Bowden, Stuart (Thesis advisor) / Schroder, Dieter (Committee member) / Honsberg, Christiana (Committee member) / Roedel, Ronald (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2013
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description
Microwave dielectrics are widely used to make resonators and filters in telecommunication systems. The production of thin films with high dielectric constant and low loss could potentially enable a marked reduction in the size of devices and systems. However, studies of these materials in thin film form are very sparse. In this research, experiments were carried out on practical high-performance dielectrics including ZrTiO4-ZnNb2O6 (ZTZN) and Ba(Co,Zn)1/3Nb2/3O3 (BCZN) with high dielectric constant and low loss tangent. Thin films were deposited by laser ablation on various substrates, with a systematical study of growth conditions like substrate temperature, oxygen pressure and annealing to optimize the film quality, and the compositional, microstructural, optical and electric properties were characterized. The deposited ZTZN films were randomly oriented polycrystalline on Si substrate and textured on MgO substrate with a tetragonal lattice change at elevated temperature. The BCZN films deposited on MgO substrate showed superior film quality relative to that on other substrates, which grow epitaxially with an orientation of (001) // MgO (001) and (100) // MgO (100) when substrate temperature was above 500 oC. In-situ annealing at growth temperature in 200 mTorr oxygen pressure was found to enhance the quality of the films, reducing the peak width of the X-ray Diffraction (XRD) rocking curve to 0.53o and the χmin of channeling Rutherford Backscattering Spectrometry (RBS) to 8.8% when grown at 800oC. Atomic Force Microscopy (AFM) was used to study the topography and found a monotonic decrease in the surface roughness when the growth temperature increased. Optical absorption and transmission measurements were used to determine the energy bandgap and the refractive index respectively. A low-frequency dielectric constant of 34 was measured using a planar interdigital measurement structure. The resistivity of the film is ~3×1010 ohm·cm at room temperature and has an activation energy of thermal activated current of 0.66 eV.
ContributorsLi, You (Author) / Newman, Nathan (Thesis advisor) / Alford, Terry (Committee member) / Singh, Rakesh (Committee member) / Arizona State University (Publisher)
Created2013
Description
Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2013
Description
Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.
ContributorsFallah-Adl, Ali (Author) / Tasooji, Amaneh (Thesis advisor) / Krause, Stephen (Committee member) / Alford, Terry (Committee member) / Jiang, Hanqing (Committee member) / Mahajan, Ravi (Committee member) / Arizona State University (Publisher)
Created2013
Description
Rapid technology scaling, the main driver of the power and performance improvements of computing solutions, has also rendered our computing systems extremely susceptible to transient errors called soft errors. Among the arsenal of techniques to protect computation from soft errors, Control Flow Checking (CFC) based techniques have gained a reputation of effective, yet low-cost protection mechanism. The basic idea is that, there is a high probability that a soft-fault in program execution will eventually alter the control flow of the program. Therefore just by making sure that the control flow of the program is correct, significant protection can be achieved. More than a dozen techniques for CFC have been developed over the last several decades, ranging from hardware techniques, software techniques, and hardware-software hybrid techniques as well. Our analysis shows that existing CFC techniques are not only ineffective in protecting from soft errors, but cause additional power and performance overheads. For this analysis, we develop and validate a simulation based experimental setup to accurately and quantitatively estimate the architectural vulnerability of a program execution on a processor micro-architecture. We model the protection achieved by various state-of-the-art CFC techniques in this quantitative vulnerability estimation setup, and find out that software only CFC protection schemes (CFCSS, CFCSS+NA, CEDA) increase system vulnerability by 18% to 21% with 17% to 38% performance overhead. Hybrid CFC protection (CFEDC) increases vulnerability by 5%, while the vulnerability remains almost the same for hardware only CFC protection (CFCET); notwithstanding the hardware overheads of design cost, area, and power incurred in the hardware modifications required for their implementations.
ContributorsRhisheekesan, Abhishek (Author) / Shrivastava, Aviral (Thesis advisor) / Colbourn, Charles Joseph (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2013
Description
We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures. Software Managed Manycore (SMM) architectures emerge as a solution. They have scalable memory design in which each core has direct access to only its local scratchpad memory, and any data transfers to/from other memories must be done explicitly in the application using Direct Memory Access (DMA) commands. Lack of automatic memory management in the hardware makes such architectures extremely power-efficient, but they also become difficult to program. If the code/data of the task mapped onto a core cannot fit in the local scratchpad memory, then DMA calls must be added to bring in the code/data before it is required, and it may need to be evicted after its use. However, doing this adds a lot of complexity to the programmer's job. Now programmers must worry about data management, on top of worrying about the functional correctness of the program - which is already quite complex. This dissertation presents a comprehensive compiler and runtime integration to automatically manage the code and data of each task in the limited local memory of the core. We firstly developed a Complete Circular Stack Management. It manages stack frames between the local memory and the main memory, and addresses the stack pointer problem as well. Though it works, we found we could further optimize the management for most cases. Thus a Smart Stack Data Management (SSDM) is provided. In this work, we formulate the stack data management problem and propose a greedy algorithm for the same. Later on, we propose a general cost estimation algorithm, based on which CMSM heuristic for code mapping problem is developed. Finally, heap data is dynamic in nature and therefore it is hard to manage it. We provide two schemes to manage unlimited amount of heap data in constant sized region in the local memory. In addition to those separate schemes for different kinds of data, we also provide a memory partition methodology.
ContributorsBai, Ke (Author) / Shrivastava, Aviral (Thesis advisor) / Chatha, Karamvir (Committee member) / Xue, Guoliang (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT Along with the fast development of science and technology, the studied materials are becoming more complicated and smaller. All these achievements have advanced with the fast development of powerful tools currently, such as Scanning electron microscopy (SEM), Focused Ion Beam (FIB), Transmission electron microscopy (TEM), Energy dispersive X-ray spectroscopy (EDX), Electron energy loss spectroscopy (EELS) and so on. SiTiO3 thin film, which is grown on Si (100) single crystals, attracts a lot of interest in its structural and electronic properties close to its interface. Valence EELS is used to investigate the Plasmon excitations of the ultrathin SrTiO3 thin film which is sandwiched between amorphous Si and crystalline Si layers. On the other hand, theoretical simulations based on dielectric functions have been done to interpret the experimental results. Our findings demonstrate the value of valence electron energy-loss spectroscopy in detecting a local change in the effective electron mass. Recently it is reported that ZnO-LiYbO2 hybrid phosphor is an efficient UV-infrared convertor for silicon solar cell but the mechanism is still not very clear. The microstructure of Li and Yb co-doped ZnO has been studied by SEM and EDX, and our results suggest that a reaction (or diffusion) zone is very likely to exist between LiYbO2 and ZnO. Such diffusion regions may be responsible for the enhanced infrared emission in the Yb and Li co-doped ZnO. Furthermore, to help us study the diffusion zone under TEM in future, the radiation damage on synthesized LiYbO2 has been studied at first, and then the electronic structure of the synthesized LiYbO2 is compared with Yb2O3 experimentally and theoretically, by EELS and FEFF8 respectively.
ContributorsYang, Bo (Author) / Alford, Terry (Thesis advisor) / Jiang, Nan (Committee member) / Theodore, N. David (Committee member) / Arizona State University (Publisher)
Created2013
Description
In this thesis we deal with the problem of temporal logic robustness estimation. We present a dynamic programming algorithm for the robust estimation problem of Metric Temporal Logic (MTL) formulas regarding a finite trace of time stated sequence. This algorithm not only tests if the MTL specification is satisfied by the given input which is a finite system trajectory, but also quantifies to what extend does the sequence satisfies or violates the MTL specification. The implementation of the algorithm is the DP-TALIRO toolbox for MATLAB. Currently it is used as the temporal logic robust computing engine of S-TALIRO which is a tool for MATLAB searching for trajectories of minimal robustness in Simulink/ Stateflow. DP-TALIRO is expected to have near linear running time and constant memory requirement depending on the structure of the MTL formula. DP-TALIRO toolbox also integrates new features not supported in its ancestor FW-TALIRO such as parameter replacement, most related iteration and most related predicate. A derivative of DP-TALIRO which is DP-T-TALIRO is also addressed in this thesis which applies dynamic programming algorithm for time robustness computation. We test the running time of DP-TALIRO and compare it with FW-TALIRO. Finally, we present an application where DP-TALIRO is used as the robustness computation core of S-TALIRO for a parameter estimation problem.
ContributorsYang, Hengyi (Author) / Fainekos, Georgios (Thesis advisor) / Sarjoughian, Hessam S. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2013