ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Barnaby, Hugh
Description
There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.
A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.
ContributorsBharadwaj, Vineeth (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2014
Description
VCO as a ubiquitous circuit in many systems is highly demanding for the phase noises. Lowering the noise migrated from the power supply has been the trending topics for many years. Considering the Ring Oscillator(RO) based VCO is more sensitive to the supply noise, it is more significant to find out a useful technique to reduce the supply noise. Among the conventional supply noise reduction techniques such as filtering, channel length adjusting for the transistors, and the current noise mutual canceling, the new feature of the 28nm UTBB-FD-SOI process launched by the ST semiconductor offered a new method to reduce the noise, which is realized by allowing the circuit designer to dynamically control the threshold voltage. In this thesis, a new structure of the linear coarse-fine VCO with 1V supply voltage is designed for the ring typed VCO. The structure is also designed to be flexible to tune the frequency coverage by the fine and coarse tunable on-board resistors. The thesis has given the model of the phase noise reduction method. The model has also been proved to be meaningful with the newly designed VCO circuit. For instances, given 1μV/√Hz white noise coupled on the supply, the 3GHz VCO can have a more than 7dBc/Hz phase noise lowering at the 10MHz frequency offset.
ContributorsTang, Miao (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2018
Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013