ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- Creators: Vasileska, Dragica
Description
GaN high electron mobility transistors (HEMTs) based on the III-V nitride material system have been under extensive investigation because of their superb performance as high power RF devices. Two dimensional electron gas(2-DEG) with charge density ten times higher than that of GaAs-based HEMT and mobility much higher than Si enables a low on-resistance required for RF devices. Self-heating issues with GaN HEMT and lack of understanding of various phenomena are hindering their widespread commercial development. There is a need to understand device operation by developing a model which could be used to optimize electrical and thermal characteristics of GaN HEMT design for high power and high frequency operation. In this thesis work a physical simulation model of AlGaN/GaN HEMT is developed using commercially available software ATLAS from SILVACO Int. based on the energy balance/hydrodynamic carrier transport equations. The model is calibrated against experimental data. Transfer and output characteristics are the key focus in the analysis along with saturation drain current. The resultant IV curves showed a close correspondence with experimental results. Various combinations of electron mobility, velocity saturation, momentum and energy relaxation times and gate work functions were attempted to improve IV curve correlation. Thermal effects were also investigated to get a better understanding on the role of self-heating effects on the electrical characteristics of GaN HEMTs. The temperature profiles across the device were observed. Hot spots were found along the channel in the gate-drain spacing. These preliminary results indicate that the thermal effects do have an impact on the electrical device characteristics at large biases even though the amount of self-heating is underestimated with respect to thermal particle-based simulations that solve the energy balance equations for acoustic and optical phonons as well (thus take proper account of the formation of the hot-spot). The decrease in drain current is due to decrease in saturation carrier velocity. The necessity of including hydrodynamic/energy balance transport models for accurate simulations is demonstrated. Possible ways for improving model accuracy are discussed in conjunction with future research.
ContributorsChowdhury, Towhid (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Zinc oxide (ZnO), a naturally n-type semiconductor has been identified as a promising candidate to replace indium tin oxide (ITO) as the transparent electrode in solar cells, because of its wide bandgap (3.37 eV), abundant source materials and suitable refractive index (2.0 at 600 nm). Spray deposition is a convenient and low cost technique for large area and uniform deposition of semiconductor thin films. In particular, it provides an easier way to dope the film by simply adding the dopant precursor into the starting solution. In order to reduce the resistivity of undoped ZnO, many works have been done by doping in the ZnO with either group IIIA elements or VIIA elements using spray pyrolysis. However, the resistivity is still too high to meet TCO's resistivity requirement. In the present work, a novel co-spray deposition technique is developed to bypass a fundamental limitation in the conventional spray deposition technique, i.e. the deposition of metal oxides from incompatible precursors in the starting solution. With this technique, ZnO films codoped with one cationic dopant, Al, Cr, or Fe, and an anionic dopant, F, have been successfully synthesized, in which F is incompatible with all these three cationic dopants. Two starting solutions were prepared and co-sprayed through two separate spray heads. One solution contained only the F precursor, NH 4F. The second solution contained the Zn and one cationic dopant precursors, Zn(O 2CCH 3) 2 and AlCl 3, CrCl 3, or FeCl 3. The deposition was carried out at 500 °C; on soda-lime glass in air. Compared to singly-doped ZnO thin films, codoped ZnO samples showed better electrical properties. Besides, a minimum sheet resistance, 55.4 Ω/sq, was obtained for Al and F codoped ZnO films after vacuum annealing at 400 °C;, which was lower than singly-doped ZnO with either Al or F. The transmittance for the Al and F codoped ZnO samples was above 90% in the visible range. This co-spray deposition technique provides a simple and cost-effective way to synthesize metal oxides from incompatible precursors with improved properties.
ContributorsZhou, Bin (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Hydrogen sulfide (H2S) has been identified as a potential ingredient for grain boundary passivation of multicrystalline silicon. Sulfur is already established as a good surface passivation material for crystalline silicon (c-Si). Sulfur can be used both from solution and hydrogen sulfide gas. For multicrystalline silicon (mc-Si) solar cells, increasing efficiency is a major challenge because passivation of mc-Si wafers is more difficult due to its randomly orientated crystal grains and the principal source of recombination is contributed by the defects in the bulk of the wafer and surface.
In this work, a new technique for grain boundary passivation for multicrystalline silicon using hydrogen sulfide has been developed which is accompanied by a compatible Aluminum oxide (Al2O3) surface passivation. Minority carrier lifetime measurement of the passivated samples has been performed and the analysis shows that success has been achieved in terms of passivation and compared to already existing hydrogen passivation, hydrogen sulfide passivation is actually better. Also the surface passivation by Al2O3 helps to increase the lifetime even more after post-annealing and this helps to attain stability for the bulk passivated samples. Minority carrier lifetime is directly related to the internal quantum efficiency of solar cells. Incorporation of this technique in making mc-Si solar cells is supposed to result in higher efficiency cells. Additional research is required in this field for the use of this technique in commercial solar cells.
In this work, a new technique for grain boundary passivation for multicrystalline silicon using hydrogen sulfide has been developed which is accompanied by a compatible Aluminum oxide (Al2O3) surface passivation. Minority carrier lifetime measurement of the passivated samples has been performed and the analysis shows that success has been achieved in terms of passivation and compared to already existing hydrogen passivation, hydrogen sulfide passivation is actually better. Also the surface passivation by Al2O3 helps to increase the lifetime even more after post-annealing and this helps to attain stability for the bulk passivated samples. Minority carrier lifetime is directly related to the internal quantum efficiency of solar cells. Incorporation of this technique in making mc-Si solar cells is supposed to result in higher efficiency cells. Additional research is required in this field for the use of this technique in commercial solar cells.
ContributorsSaha, Arunodoy, Ph.D (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2014
Description
In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET.
ContributorsAshraf, Nabil Shovon (Author) / Vasileska, Dragica (Thesis advisor) / Schroder, Dieter (Committee member) / Goodnick, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Development of New Front Side Metallization Method of Aluminum Electroplating for Silicon Solar Cell
Description
In this thesis, the methods of aluminum electroplating in an ionic liquid for silicon solar cell front side metallization were studied. It focused on replacing the current silver screen printing with an alternative metallization technology using a low-cost Earth-abundant metal for mass production, due to the high cost and limited availability of silver. A conventional aluminum electroplating method was employed for silicon solar cells fabrication on both p-type and n-type substrates. The highest efficiency of 17.9% was achieved in the n-type solar cell with a rear junction, which is comparable to that of the same structure cell with screen printed silver electrodes from industrial production lines. It also showed better spiking resistant performance than the common structure p-type solar cell. Further efforts were put on the development of a novel light-induced plating of aluminum technique. The aluminum was deposited directly on a silicon substrate without the assistance of a conductive seed layer, thus simplified and reduced the process cost. The plated aluminum has good adhesion to the silicon surface with the resistivity as low as 4×10–6 -cm. A new demo tool was designed and set up for the light-induced plating experiment, aiming to utilize this technique in large-size solar cells fabrication and mass production. Besides the metallization methods, a comprehensive sensitivity analysis for the efficiency dispersion in the production of crystalline-Si solar cells was presented based on numerical simulations. Temperature variation in the diffusion furnace was the most significant cause of the efficiency dispersion. It was concluded that a narrow efficiency range of ±0.5% absolute is achievable if the emitter diffusion temperature is confined to a 13˚C window, while other cell parameters vary within their normal windows. Possible methods to minimize temperature variation in emitter diffusion were proposed.
ContributorsWang, Laidong (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2018
Description
To date, the most popular and dominant material for commercial solar cells is
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
ContributorsSun, Wen-Cheng (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
Sb-based type-II superlattices (T2SLs) are potential alternative to HgCdTe for infrared detection due to their low manufacturing cost, good uniformity, high structural stability, and suppressed Auger recombination. The emerging InAs/InAsSb T2SLs have minority carrier lifetimes 1-2 orders of magnitude longer than those of the well-studied InAs/InGaSb T2SLs, and therefore have the potential to achieve photodetectors with higher performance. This work develops a novel method to measure the minority carrier lifetimes in infrared materials, and reports a comprehensive characterization of minority carrier lifetime and transport in InAs/InAsSb T2SLs at temperatures below 77 K.
A real-time baseline correction (RBC) method for minority carrier lifetime measurement is developed by upgrading a conventional boxcar-based time-resolved photoluminescence (TRPL) experimental system that suffers from low signal-to-noise ratio due to strong low frequency noise. The key is to modify the impulse response of the conventional TRPL system, and therefore the system becomes less sensitive to the dominant noise. Using this RBC method, the signal-to-noise ratio is improved by 2 orders of magnitude.
A record long minority carrier lifetime of 12.8 μs is observed in a high-quality mid-wavelength infrared InAs/InAsSb T2SLs at 15 K. It is further discovered that this long lifetime is partially due to strong carrier localization, which is revealed by temperature-dependent photoluminescence (PL) and TRPL measurements for InAs/InAsSb T2SLs with different period thicknesses. Moreover, the PL and TRPL results suggest that the atomic layer thickness variation is the main origin of carrier localization, which is further confirmed by a calculation using transfer matrix method.
To study the impact of the carrier localization on the device performance of InAs/InAsSb photodetectors, minority hole diffusion lengths are determined by the simulation of external quantum efficiency (EQE). A comparative study shows that carrier localization has negligible effect on the minority hole diffusion length in InAs/InAsSb T2SLs, and the long minority carrier lifetimes enhanced by carrier localization is not beneficial for photodetector operation.
A real-time baseline correction (RBC) method for minority carrier lifetime measurement is developed by upgrading a conventional boxcar-based time-resolved photoluminescence (TRPL) experimental system that suffers from low signal-to-noise ratio due to strong low frequency noise. The key is to modify the impulse response of the conventional TRPL system, and therefore the system becomes less sensitive to the dominant noise. Using this RBC method, the signal-to-noise ratio is improved by 2 orders of magnitude.
A record long minority carrier lifetime of 12.8 μs is observed in a high-quality mid-wavelength infrared InAs/InAsSb T2SLs at 15 K. It is further discovered that this long lifetime is partially due to strong carrier localization, which is revealed by temperature-dependent photoluminescence (PL) and TRPL measurements for InAs/InAsSb T2SLs with different period thicknesses. Moreover, the PL and TRPL results suggest that the atomic layer thickness variation is the main origin of carrier localization, which is further confirmed by a calculation using transfer matrix method.
To study the impact of the carrier localization on the device performance of InAs/InAsSb photodetectors, minority hole diffusion lengths are determined by the simulation of external quantum efficiency (EQE). A comparative study shows that carrier localization has negligible effect on the minority hole diffusion length in InAs/InAsSb T2SLs, and the long minority carrier lifetimes enhanced by carrier localization is not beneficial for photodetector operation.
ContributorsLin, Zhiyuan (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Johnson, Shane (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
This work demonstrates novel nBn photodetectors including mid-wave infrared (MWIR) nBn photodetectors based on InAs/InAsSb type-II superlattices (T2SLs) with charge as the output signal, and visible nBn photodetectors based on CdTe with current output. Furthermore, visible/MWIR two-color photodetectors (2CPDs) are fabricated through monolithic integration of the CdTe nBn photodetector and an InSb photodiode.
The MWIR nBn photodetectors have a potential well for holes present in the barrier layer. At low voltages of < −0.2 V, which ensure low dark current <10-5 A/cm2 at 77 K, photogenerated holes are collected in this well with a storage lifetime of 40 s. This charge collection process is an in-device signal integration process that reduces the random noise significantly. Since the stored holes can be readout laterally as in charge-coupled devices, it is therefore possible to make charge-output nBn with much lower noise than conventional current-output nBn photodetectors.
The visible nBn photodetectors have a CdTe absorber layer and a ZnTe barrier layer with an aligned valence band edge. By using a novel ITO/undoped-CdTe top contact design, it has achieved a high specific detectivity of 3×1013 cm-Hz1/2/W at room temperature. Particularly, this CdTe nBn photodetector grown on InSb substrates enables the monolithic integration of CdTe and InSb photodetectors, and provides a platform to study in-depth device physics of nBn photodetectors at room temperature.
Furthermore, the visible/MWIR 2CPD has been developed by the monolithic integration of the CdTe nBn and an InSb photodiode through an n-CdTe/p-InSb tunnel junction. At 77 K, the photoresponse of the 2CPD can be switched between a 1-5.5 μm MWIR band and a 350-780 nm visible band by illuminating the device with an external light source or not, and applying with proper voltages. Under optimum conditions, the 2CPD has achieved a MWIR peak responsivity of 0.75 A/W with a band rejection ratio (BRR) of 52 dB, and a visible peak responsivity of 0.3 A/W with a BRR of 18 dB. This 2CPD has enabled future compact image sensors with high fill-factor and responsivity switchable between visible and MWIR colors.
The MWIR nBn photodetectors have a potential well for holes present in the barrier layer. At low voltages of < −0.2 V, which ensure low dark current <10-5 A/cm2 at 77 K, photogenerated holes are collected in this well with a storage lifetime of 40 s. This charge collection process is an in-device signal integration process that reduces the random noise significantly. Since the stored holes can be readout laterally as in charge-coupled devices, it is therefore possible to make charge-output nBn with much lower noise than conventional current-output nBn photodetectors.
The visible nBn photodetectors have a CdTe absorber layer and a ZnTe barrier layer with an aligned valence band edge. By using a novel ITO/undoped-CdTe top contact design, it has achieved a high specific detectivity of 3×1013 cm-Hz1/2/W at room temperature. Particularly, this CdTe nBn photodetector grown on InSb substrates enables the monolithic integration of CdTe and InSb photodetectors, and provides a platform to study in-depth device physics of nBn photodetectors at room temperature.
Furthermore, the visible/MWIR 2CPD has been developed by the monolithic integration of the CdTe nBn and an InSb photodiode through an n-CdTe/p-InSb tunnel junction. At 77 K, the photoresponse of the 2CPD can be switched between a 1-5.5 μm MWIR band and a 350-780 nm visible band by illuminating the device with an external light source or not, and applying with proper voltages. Under optimum conditions, the 2CPD has achieved a MWIR peak responsivity of 0.75 A/W with a band rejection ratio (BRR) of 52 dB, and a visible peak responsivity of 0.3 A/W with a BRR of 18 dB. This 2CPD has enabled future compact image sensors with high fill-factor and responsivity switchable between visible and MWIR colors.
ContributorsHe, Zhaoyu (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2016
Description
As the single-junction silicon solar cell is approaching its theoretical efficiency limits, the loss from shading and resistance is gaining increasing attention. The metal grid pattern may cause an efficiency loss up to 1–3%abs (absolute percentage) depending on the grid’s materials and structure.Many attempts have been proposed to reduce the loss caused by the contacts and module. Among them, the monolithic solar cell, which is a solar cell with multiple string cells on the same wafer and connected in a series, presents advantages of low output current, busbar-free contact, minimized interconnection space, and ohmic loss reduction. However, this structure also introduces a lateral forward bias current through the base region, which severely degrades the cell’s performance. In addition, this interconnection in the base region has partially shunted certain solar cells in the monolithic cell, which created a mismatch between string cells.
For the last few decades, researchers have used different methods such as etching trenches or enlarging the distance between the neighboring string cells to solve this problem. However, these methods were both ineffective and defective.
In this work, a novel method of suppressing the lateral forward bias current is proposed. By adding a very high surface recombination to the mid-region between the string cells, the carrier density in the mid-region can be decreased close to the doping density. Thus, the resistivity in the mid-region can be increased tenfold or more. As a result, the lateral forward bias current is greatly reduced.
Other methods to reduce lateral forward bias current include optimizing the width of the mid-region, shading the mid-region, reducing the base doping and base thickness which can be used to reduce the mismatch as well.
Another method has been proposed to calculate the minimum efficiency loss of a monolithic cell compared to the baseline solar cell. As a result, the monolithic cell could potentially gain more advantages over the baseline solar cells with a thinner and low-doped wafer.
A monolithic solar cell with innovative designs is presented in this work which shows an efficiency that is potentially higher than that of normal solar cells.
ContributorsXue, Shujian (Author) / Bowden, Studart (Thesis advisor) / Goodnick, Stephen (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022