ETDs

This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.

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A CMOS sigma-delta digital intermediate frequency to radio frequency transmitter

Description
During the last decades the development of the transistor and its continuous down-scaling allowed the appearance of cost effective wireless communication systems. New generation wideband wireless mobile systems demand high linearity, low power consumption and the low cost devices. Traditional RF systems are mainly analog-based circuitry. Contrary to digital circuits,…

During the last decades the development of the transistor and its continuous down-scaling allowed the appearance of cost effective wireless communication systems. New generation wideband wireless mobile systems demand high linearity, low power consumption and the low cost devices. Traditional RF systems are mainly analog-based circuitry. Contrary to digital circuits, the technology scaling results in reduction on the maximum voltage swing which makes RF design very challenging. Pushing the interface between the digital and analog boundary of the RF systems closer to the antenna becomes an attractive trend for modern RF devices. In order to take full advantages of the deep submicron CMOS technologies and digital signal processing (DSP), there is a strong trend towards the development of digital transmitter where the RF upconversion is part of the digital-to-analog conversion (DAC). This thesis presents a new digital intermediate frequency (IF) to RF transmitter for 2GHz wideband code division multiple access (W-CDMA). The proposed transmitter integrates a 3-level digital IF current-steering cell, an up-conversion mixer with a tuned load and an RF variable gain amplifier (RF VGA) with an embedded finite impulse response (FIR) reconstruction filter in the up-conversion path. A 4th-order 1.5-bit IF bandpass sigma delta modulator (BP SDM) is designed to support in-band SNR while the out-of-band quantization noise due to the noise shaping is suppressed by the embedded reconstruction filter to meet spectrum emission mask and ACPR requirements. The RF VGA provides 50dB power scaling in 10-dB steps with less than 1dB gain error. The design is fabricated in a 0.18um CMOS technology with a total core area of 0.8 x 1.6 mm2. The IC delivers 0dBm output power at 2GHz and it draws approximately 120mA from a 1.8V DC supply at the maximum output power. The measurement results proved that a digital-intensive digital IF to RF converter architecture can be successfully employed for WCDMA transmitter application.
ContributorsHan, Yongping (Author) / Kiaei, Sayfe (Thesis advisor) / Yu, Hongyu (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
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Design of a continuous time sigma delta analog-to-digital converter for operation in extreme environments

Description
In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta…

In this work, a high resolution analog-to-digital converter (ADC) for use in harsh environments is presented. The ADC is implemented in bulk CMOS technology and is intended for space exploration, mining and automotive applications with a range of temperature variation in excess of 250°C. A continuous time (CT) sigma delta modulator employing a cascade of integrators with feed forward (CIFF) architecture in a single feedback loop topology is used for implementing the ADC. In order to enable operation in the intended application environments, an RC time constant tuning engine is proposed. The tuning engine is used to maintain linearity of a 10 ksps 20 bit continuous time sigma delta ADC designed for spectroscopy applications in space. The proposed circuit which is based on master slave architecture automatically selects on chip resistors to control RC time constants to an accuracy range of ±5% to ±1%. The tuning range, tuning accuracy and circuit non-idealities are analyzed theoretically. To verify the concept, an experimental chip was fabricated in JAZZ .18µm 1.8V CMOS technology. The tuning engine which occupies an area of .065mm2; consists of only an integrator, a comparator and a shift register. It can achieve a signal to noise and distortion ratio (SNDR) greater than 120dB over a ±40% tuning range.
ContributorsAnabtawi, Nijad (Author) / Barnaby, Hugh (Thesis advisor) / Vermeire, Bert (Committee member) / Gildenblat, Gennady (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Created2011