ETDs

This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.

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Design, modeling and simulation of nanoscale optoelectronic devices: semiconductor nano-lasers and plasmonic waveguides

Description
This thesis summarizes the research work carried out on design, modeling and simulation of semiconductor nanophotonic devices. The research includes design of nanowire (NW) lasers, modeling of active plasmonic waveguides, design of plasmonic nano-lasers, and design of all-semiconductor plasmonic systems. For the NW part, a comparative study of electrical injection…

This thesis summarizes the research work carried out on design, modeling and simulation of semiconductor nanophotonic devices. The research includes design of nanowire (NW) lasers, modeling of active plasmonic waveguides, design of plasmonic nano-lasers, and design of all-semiconductor plasmonic systems. For the NW part, a comparative study of electrical injection in the longitudinal p-i-n and coaxial p-n core-shell NWs was performed. It is found that high density carriers can be efficiently injected into and confined in the core-shell structure. The required bias voltage and doping concentrations in the core-shell structure are smaller than those in the longitudinal p-i-n structure. A new device structure with core-shell configuration at the p and n contact regions for electrically driven single NW laser was proposed. Through a comprehensive design trade-off between threshold gain and threshold voltage, room temperature lasing has been proved in the laser with low threshold current and large output efficiency. For the plasmonic part, the propagation of surface plasmon polariton (SPP) in a metal-semiconductor-metal structure where semiconductor is highly excited to have an optical gain was investigated. It is shown that near the resonance the SPP mode experiences an unexpected giant modal gain that is 1000 times of the material gain in the semiconductor and the corresponding confinement factor is as high as 105. The physical origin of the giant modal gain is the slowing down of the average energy propagation in the structure. Secondly, SPP modes lasing in a metal-insulator-semiconductor multi-layer structure was investigated. It is shown that the lasing threshold can be reduced by structural optimization. A specific design example was optimized using AlGaAs/GaAs/AlGaAs single quantum well sandwiched between silver layers. This cavity has a physical volume of 1.5×10-4 λ03 which is the smallest nanolaser reported so far. Finally, the all-semiconductor based plasmonics was studied. It is found that InAs is superior to other common semiconductors for plasmonic application in mid-infrared range. A plasmonic system made of InAs, GaSb and AlSb layers, consisting of a plasmonic source, waveguide and detector was proposed. This on-chip integrated system is realizable in a single epitaxial growth process.
ContributorsLi, Debin (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Balanis, Constantine A (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
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Compact modeling and simulation for digital circuit aging

Description
Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under…

Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage. With CMOS technology scaling, design for reliability has become an important step in the design cycle, and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI induced delay shifts in logic paths are asymmetric in nature, as opposed to averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this report, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of the simulation flow include: (1) accurate modeling of aging induced delay shift due to threshold voltage (Vth) shift using only the delay dependence on supply voltage from cell library; (2) simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; (3) setup and hold timing violations due to NBTI aging in logic and clock buffer are investigated in sequential circuits and (4) proposed framework is tested in VLSI applications such DDR memory circuits. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45nm Nangate standard cell library characterized using predictive technology models. Our proposed design margin assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.
ContributorsVelamala, Jyothi Bhaskarr (Author) / Cao, Yu (Thesis advisor) / Clark, Lawrence (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012