ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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- All Subjects: Electrical Engineering
Description
Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high sensitivity and low noise. The major application of fluxgate sensors is in magnetometers for the measurement of earth's magnetic field. Magnetometers are used in navigation systems and electronic compasses. Fluxgate sensors can also be used to measure high DC currents. Integrated micro-fluxgate sensors have been developed in recent years. These sensors have much lower power consumption and area compared to their PCB counterparts. The output voltage of micro-fluxgate sensors is very low which makes the analog front end more complex and results in an increase in power consumption of the system. In this thesis a new analog front-end circuit for micro-fluxgate sensors is developed. This analog front-end circuit uses charge pump based excitation circuit and phase delay based read-out chain. With these two features the power consumption of analog front-end is reduced. The output is digital and it is immune to amplitude noise at the output of the sensor. Digital output is produced without using an ADC. A SPICE model of micro-fluxgate sensor is used to verify the operation of the analog front-end and the simulation results show very good linearity.
ContributorsPappu, Karthik (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis summarizes modeling and simulation of plasmonic waveguides and nanolasers. The research includes modeling of dielectric constants of doped semiconductor as a potential plasmonic material, simulation of plasmonic waveguides with different configurations and geometries, simulation and design of plasmonic nanolasers. In the doped semiconductor part, a more accurate model accounting for dielectric constant of doped InAs was proposed. In the model, Interband transitions accounted for by Adachi's model considering Burstein-Moss effect and free electron effect governed by Drude model dominate in different spectral regions. For plasmonic waveguide part, Insulator-Metal-Insulator (IMI) waveguide, silver nanowire waveguide with and without substrate, Metal-Semiconductor-Metal (MSM) waveguide and Metal-Insulator-Semiconductor-Insulator-Metal (MISIM) waveguide were investigated respectively. Modal analysis was given for each part. Lastly, a comparative study of plasmonic and optical modes in an MSM disk cavity was performed by FDTD simulation for room temperature at the telecommunication wavelength. The results show quantitatively that plasmonic modes have advantages over optical modes in the scalability down to small size and the cavity Quantum Electrodynamics(QED) effects due to the possibility of breaking the diffraction limit. Surprisingly for lasing characteristics, though plasmonic modes have large loss as expected, minimal achievable threshold can be attained for whispering gallery plasmonic modes with azimuthal number of 2 by optimizing cavity design at 1.55µm due to interplay of metal loss and radiation loss.
ContributorsWang, Haotong (Author) / Ning, Cunzheng (Thesis advisor) / Palais, Joseph (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2014
Description
Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation. In this study, vertical Ge and Si nanowire Schottky diodes have been fabricated using bottom-up vapor-liquid-solid (VLS) and top-down reactive ion etching (RIE) approaches respectively. VLS growth yields nanowires with atomically smooth sidewalls at sub-50 nm diameters but suffers from the problem that the doping increases radially outwards from the core of the devices. RIE is much faster than VLS and does not suffer from the problem of non-uniform doping. However, it yields nanowires with rougher sidewalls and gets exceedingly inefficient in yielding vertical nanowires for diameters below 50 nm. The I-V characteristics of both Ge and Si nanowire diodes cannot be adequately fit by the thermionic emission model. Annealing in forming gas which passivates dangling bonds on the nanowire surface is shown to have a considerable impact on the current through the Si nanowire diodes indicating that fixed charges and traps on the surface of the devices play a major role in determining their electrical behavior. Also, due to the vertical geometry of the nanowire diodes, electric field lines originating from the metal and terminating on their sidewalls can directly modulate their conductivity. Both these effects have to be included in the model aimed at predicting the current through vertical nanowire diodes. This study shows that the current through vertical nanowire diodes cannot be predicted accurately using the thermionic emission model which is suitable for planar devices and identifies the factors needed to build a comprehensive analytical model for predicting the current through vertically oriented nanowire diodes.
ContributorsChandra, Nishant (Author) / Goodnick, Stephen M (Thesis advisor) / Tracy, Clarence J. (Committee member) / Yu, Hongbin (Committee member) / Ferry, David K. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Zinc oxide (ZnO), a naturally n-type semiconductor has been identified as a promising candidate to replace indium tin oxide (ITO) as the transparent electrode in solar cells, because of its wide bandgap (3.37 eV), abundant source materials and suitable refractive index (2.0 at 600 nm). Spray deposition is a convenient and low cost technique for large area and uniform deposition of semiconductor thin films. In particular, it provides an easier way to dope the film by simply adding the dopant precursor into the starting solution. In order to reduce the resistivity of undoped ZnO, many works have been done by doping in the ZnO with either group IIIA elements or VIIA elements using spray pyrolysis. However, the resistivity is still too high to meet TCO's resistivity requirement. In the present work, a novel co-spray deposition technique is developed to bypass a fundamental limitation in the conventional spray deposition technique, i.e. the deposition of metal oxides from incompatible precursors in the starting solution. With this technique, ZnO films codoped with one cationic dopant, Al, Cr, or Fe, and an anionic dopant, F, have been successfully synthesized, in which F is incompatible with all these three cationic dopants. Two starting solutions were prepared and co-sprayed through two separate spray heads. One solution contained only the F precursor, NH 4F. The second solution contained the Zn and one cationic dopant precursors, Zn(O 2CCH 3) 2 and AlCl 3, CrCl 3, or FeCl 3. The deposition was carried out at 500 °C; on soda-lime glass in air. Compared to singly-doped ZnO thin films, codoped ZnO samples showed better electrical properties. Besides, a minimum sheet resistance, 55.4 Ω/sq, was obtained for Al and F codoped ZnO films after vacuum annealing at 400 °C;, which was lower than singly-doped ZnO with either Al or F. The transmittance for the Al and F codoped ZnO samples was above 90% in the visible range. This co-spray deposition technique provides a simple and cost-effective way to synthesize metal oxides from incompatible precursors with improved properties.
ContributorsZhou, Bin (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Nanolasers represents the research frontier in both the areas of photonics and nanotechnology for its interesting properties in low dimension physics, its appealing prospects in integrated photonics, and other on-chip applications. In this thesis, I present my research work on fabrication and characterization of a new type of nanolasers: metallic cavity nanolasers. The last ten years witnessed a dramatic paradigm shift from pure dielectric cavity to metallic cavity in the research of nanolasers. By using low loss metals such as silver, which is highly reflective at near infrared, light can be confined in an ultra small cavity or waveguide with sub-wavelength dimensions, thus enabling sub-wavelength cavity lasers. Based on this idea, I fabricated two different kinds of metallic cavity nanolasers with rectangular and circular geometries with InGaAs as the gain material and silver as the metallic shell. The lasing wavelength is around 1.55 μm, intended for optical communication applications. Continuous wave (CW) lasing at cryogenic temperature under current injection was achieved on devices with a deep sub-wavelength physical cavity volume smaller than 0.2 λ3. Improving device fabrication process is one of the main challenges in the development of metallic cavity nanolasers due to its ultra-small size. With improved fabrication process and device design, CW lasing at room temperature was demonstrated as well on a sub-wavelength rectangular device with a physical cavity volume of 0.67 λ3. Experiments verified that a small circular nanolasers supporting TE¬01 mode can generate an azimuthal polarized laser beam, providing a compact such source under electrical injection. Sources with such polarizations could have many special applications. Study of digital modulation of circular nanolasers showed that laser noise is an important factor that will affect the data rate of the nanolaser when used as the light source in optical interconnects. For future development, improving device fabrication processes is required to improve device performance. In addition, techniques need to be developed to realize nanolaser/Si waveguide integration. In essence, resolving these two critical issues will finally pave the way for these nanolasers to be used in various practical applications.
ContributorsDing, Kang (Author) / Ning, Cun-Zheng (Thesis advisor) / Yu, Hongbin (Committee member) / Palais, Joseph (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
Description
This dissertation aims to demonstrate a new approach to fabricating solar cells for spectrum-splitting photovoltaic systems with the potential to reduce their cost and complexity of manufacturing, called Monolithically Integrated Laterally Arrayed Multiple Band gap (MILAMB) solar cells. Single crystal semiconductor alloy nanowire (NW) ensembles are grown with the alloy composition and band gap changing continuously across a broad range over the surface of a single substrate in a single, inexpensive growth step by the Dual-Gradient Method. The nanowire ensembles then serve as the absorbing materials in a set of solar cells for spectrum-splitting photovoltaic systems.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
ContributorsCaselli, Derek (Author) / Ning, Cun-Zheng (Thesis advisor) / Tao, Meng (Committee member) / Yu, Hongbin (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
Description
Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books.
ContributorsYang, Xuan (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2011
Description
A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
ContributorsSinha, Saurabh (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Yu, Hongbin (Committee member) / Christen, Jennifer B. (Committee member) / Arizona State University (Publisher)
Created2011
Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this work, I worked on the synthesis and characterization of nanowires and belts, grown using different materials, in Chemical Vapor Deposition (CVD) system with catalytic growth method. Through this thesis, I utilized the Photoluminescence (PL), Secondary Electron Microscopy (SEM), Energy Dispersive Spectroscopy (EDS) and X-ray diffraction (XRD) analyses to find out the properties of Erbium Chloride Silicate (ECS) and two segment CdS-CdSe samples. In the first part of my research, growth of very new material, Erbium Chloride Silicate (ECS), in form of core/shell Si/ECS and pure ECS nanowires, was demonstrated. This new material has very fascinating properties for new Si based photonic devices. The Erbium density in those nanowires is which is very high value compared to the other Erbium doped materials. It was shown that the luminescence peaks of ECS nanowires are very sharp and stronger than their counterparts. Furthermore, both PL and XRD peaks get sharper and stronger as growth temperature increases and this shows that crystalline quality of ECS nanowires gets better with higher temperature. In the second part, I did a very detail research for growing two segment axial nanowires or radial belts and report that the structure type mostly depends on the growth temperature. Since our final step is to create white light LEDs using single axial nanowires which have three different regions grown with distinct materials and give red, green and blue colors simultaneously, we worked on growing CdS-CdSe nanowires or belts for the first step of our aim. Those products were successfully grown and they gave two luminescence peaks with maximum 160 nm wavelength separation depending on the growth conditions. It was observed that products become more likely belt once the substrate temperature increases. Also, dominance between VLS and VS is very critical to determine the shape of the products and the substitution of CdS by CdSe is very effective; hence, CdSe growth time should be chosen accordingly. However, it was shown two segmented products can be synthesized by picking the right conditions and with very careful analyses. We also demonstrated that simultaneous two colors lasing from a single segmented belt structures is possible with strong enough-pumping-power.
ContributorsTurkdogan, Sunay (Author) / Ning, Cun-Zheng (Thesis advisor) / Tao, Meng (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012