ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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Description
The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.
ContributorsKim, Sung (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Cao, Yu (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
Obtaining local electrochemical (EC) information is extremely important for understanding basic surface reactions, and for many applications. Scanning electrochemical microscopy (SECM) can obtain local EC information by scanning a microelectrode across the surface. Although powerful, SECM is slow, the scanning microelectrode may perturb reaction and the measured signal decreases with the size of microelectrode. This thesis demonstrates a new imaging technique based on a principle that is completely different from the conventional EC detection technologies. The technique, referred to as plasmonic-based electrochemical imaging (PECI), images local EC current (both faradaic and non-faradaic) without using a scanning microelectrode. Because PECI response is an optical signal originated from surface plasmon resonance (SPR), PECI is fast and non-invasive and its signal is proportional to incident light intensity, thus does not decrease with the area of interest. A complete theory is developed in this thesis work to describe the relationship between EC current and PECI signal. EC current imaging at various fixed potentials and local cyclic voltammetry methods are developed and demonstrated with real samples. Fast imaging rate (up to 100,000 frames per second) with 0.2×3µm spatial resolution and 0.3 pA detection limit have been achieved. Several PECI applications have been developed to demonstrate the unique strengths of the new imaging technology. For example, trace particles in fingerprint is detected by PECI, a capability that cannot be achieved with the conventional EC technologies. Another example is PECI imaging of EC reaction and interfacial impedance of graphene of different thicknesses. In addition, local square wave voltammetry capability is demonstrated and applied to study local catalytic current of platinum nanoparticle microarray. This thesis also describes a related but different research project that develops a new method to measure surface charge densities of SPR sensor chips, and micro- and nano-particles. A third project of this thesis is to develop a method to expand the conventional SPR detection and imaging technology by including a waveguide mode. This innovation creates a sensitive detection of bulk index of refraction, which overcomes the limitation that the conventional SPR can probe only changes near the sensor surface within ~200 nm.
ContributorsShan, Xiaonan (Author) / Tao, Nongjian (Thesis advisor) / Chae, Junseok (Committee member) / Christen, Jennifer Blain (Committee member) / Hayes, Mark (Committee member) / Arizona State University (Publisher)
Created2011
Description
Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high sensitivity and low noise. The major application of fluxgate sensors is in magnetometers for the measurement of earth's magnetic field. Magnetometers are used in navigation systems and electronic compasses. Fluxgate sensors can also be used to measure high DC currents. Integrated micro-fluxgate sensors have been developed in recent years. These sensors have much lower power consumption and area compared to their PCB counterparts. The output voltage of micro-fluxgate sensors is very low which makes the analog front end more complex and results in an increase in power consumption of the system. In this thesis a new analog front-end circuit for micro-fluxgate sensors is developed. This analog front-end circuit uses charge pump based excitation circuit and phase delay based read-out chain. With these two features the power consumption of analog front-end is reduced. The output is digital and it is immune to amplitude noise at the output of the sensor. Digital output is produced without using an ADC. A SPICE model of micro-fluxgate sensor is used to verify the operation of the analog front-end and the simulation results show very good linearity.
ContributorsPappu, Karthik (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Due to heterogeneity at the cellular level, single cell analysis (SCA) has become a necessity to study cellomics for the early detection of diseases like cancer. Development of single cell manipulation systems is very critical for performing SCA. In this thesis, electrorotation (ROT) chips to trap and rotate single cells using electrokinetic forces have been developed. The ROT chip mainly consists of a set of closely spaced metal electrodes (60µm interspacing between opposite electrodes) that forms a closed electric field cage (electrocage) when driven with high frequency AC voltages. Cells were flowed through a microchannel to the electrocage where they could be precisely trapped, levitated and rotated in 3-D along the axis of interest. The dielectrophoresis based ROT chip design and relevant electrokinetic effects have been simulated using COMSOL 3.4 to optimize the design parameters. Also, various semiconductor technology fabrication process steps have been developed and optimized for better yield and repeatability in the manufacture of the ROT chip. The ROT chip thus fabricated was used to characterize rotation of single cells with respect to the control parameters namely excitation voltage, frequency and cell line. The longevity of cell rotation under electric fields has been probed. Also, the Joule heating inside the ROT chip due to applied voltage has been characterized to know the thermal stress on the cells. The major advantages of the ROT chip developed are precise electrorotation of cells, simple design and straight forward fabrication process.
ContributorsSoundappa Elango, Iniyan (Author) / Meldrum, Deirdre R (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Johnson, Roger H (Committee member) / Arizona State University (Publisher)
Created2012
Description
The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold pedestal, feed through error. This thesis will discuss the importance of these parameters of a THA to the ADCs and commonly used architectures of THA. A new architecture with SiGe HBT transistors in BiCMOS 130 nm technology is presented here. The proposed topology without complicated circuitry achieves high Spurious Free Dynamic Range(SFDR) and Total Harmonic Distortion (THD).These are important figure of merits for any THA which gives a measure of non-linearity of the circuit. The proposed topology is implemented in IBM8HP 130 nm BiCMOS process combines typical emitter follower switch in bipolar THAs and output steering technique proposed in the previous work. With these techniques and the cascode transistor in the input which is used to isolate the switch from the input during the hold mode, better results have been achieved. The THA is designed to work with maximum input frequency of 250 MHz at sampling frequency of 500 MHz with input currents not more than 5mA achieving an SFDR of 78.49 dB. Simulation and results are presented, illustrating the advantages and trade-offs of the proposed topology.
ContributorsRao, Nishita Ramakrishna (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator.
ContributorsSwaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Different environmental factors, such as ultraviolet radiation (UV), relative humidity (RH) and the presence of reducing gases (acetone and ethanol), play an important role in the daily life of human beings. UV is very important in a number of areas, such as astronomy, resin curing of polymeric materials, combustion engineering, water purification, flame detection and biological effects with more recent proposals like early missile plume detection, secure space-to-space communications and pollution monitoring. RH is a very common parameter in the environment. It is essential not only for human comfort, but also for a broad spectrum of industries and technologies. There is a substantial interest in the development of RH sensors for applications in monitoring moisture level at home, in clean rooms, cryogenic processes, medical and food science, and so on. The concentration of acetone and other ketone bodies in the exhaled air can serve as an express noninvasive diagnosis of ketosis. Meanwhile, driving under the influence of alcohol is a serious traffic violation and this kind of deviant behavior causes many accidents and deaths on the highway. Therefore, the detection of ethanol in breath is usually used as a quick and reliable screening method for the sobriety checkpoint. Traditionally, semiconductor metal oxide sensors are the major candidates employed in the sensing applications mentioned above. However, they suffer from the low sensitivity, poor selectivity and huge power consumption. In this dissertation, Zinc Oxide (ZnO) based Film Bulk Acoustic Resonator (FBAR) was developed to monitor UV, RH, acetone and ethanol in the environment. FBAR generally consists of a sputtered piezoelectric thin film (ZnO/AlN) sandwiched between two electrodes. It has been well developed both as filters and as high sensitivity mass sensors in recent years. FBAR offers high sensitivity and excellent selectivity for various environment monitoring applications. As the sensing signal is in the frequency domain, FABR has the potential to be incorporated in a wireless sensor network for remote sensing. This study extended our current knowledge of FBAR and pointed out feasible directions for future exploration.
ContributorsQiu, Xiaotun (Author) / Yu, Hongyu (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Aberle, James T., 1961- (Committee member) / Jiang, Hanqing (Committee member) / Arizona State University (Publisher)
Created2011
Description
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation.
ContributorsGao, Hang (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2018
Description
Alternative computation based on neural systems on a nanoscale device are of increasing interest because of the massive parallelism and scalability they provide. Neural based computation systems also offer defect finding and self healing capabilities. Traditional Von Neumann based architectures (which separate the memory and computation units) inherently suffer from the Von Neumann bottleneck whereby the processor is limited by the number of instructions it fetches. The clock driven based Von Neumann computer survived because of technology scaling. However as transistor scaling is slowly coming to an end with channel lengths becoming a few nanometers in length, processor speeds are beginning to saturate. This lead to the development of multi-core systems which process data in parallel, with each core being based on the Von Neumann architecture.
The human brain has always been a mystery to scientists. Modern day super computers are outperformed by the human brain in certain computations. The brain occupies far less space and consumes a fraction of the power a super computer does with certain processes such as pattern recognition. Neuromorphic computing aims to mimic biological neural systems on silicon to exploit the massive parallelism that neural systems offer. Neuromorphic systems are event driven systems rather than being clock driven. One of the issues faced by neuromorphic computing was the area occupied by these circuits. With recent developments in the field of nanotechnology, memristive devices on a nanoscale have been developed and show a promising solution. Memristor based synapses can be up to three times smaller than Complementary Metal Oxide Semiconductor (CMOS) based synapses.
In this thesis, the Programmable Metallization Cell (a memristive device) is used to prove a learning algorithm known as Spike Time Dependant Plasticity (STDP). This learning algorithm is an extension to Hebb’s learning rule in which the synapses weight can be altered by the relative timing of spikes across it. The synaptic weight with the memristor will be its conductance, and CMOS oscillator based circuits will be used to produce spikes that can modulate the memristor conductance by firing with different phases differences.
The human brain has always been a mystery to scientists. Modern day super computers are outperformed by the human brain in certain computations. The brain occupies far less space and consumes a fraction of the power a super computer does with certain processes such as pattern recognition. Neuromorphic computing aims to mimic biological neural systems on silicon to exploit the massive parallelism that neural systems offer. Neuromorphic systems are event driven systems rather than being clock driven. One of the issues faced by neuromorphic computing was the area occupied by these circuits. With recent developments in the field of nanotechnology, memristive devices on a nanoscale have been developed and show a promising solution. Memristor based synapses can be up to three times smaller than Complementary Metal Oxide Semiconductor (CMOS) based synapses.
In this thesis, the Programmable Metallization Cell (a memristive device) is used to prove a learning algorithm known as Spike Time Dependant Plasticity (STDP). This learning algorithm is an extension to Hebb’s learning rule in which the synapses weight can be altered by the relative timing of spikes across it. The synaptic weight with the memristor will be its conductance, and CMOS oscillator based circuits will be used to produce spikes that can modulate the memristor conductance by firing with different phases differences.
ContributorsSivaraj, Mahraj (Author) / Barnaby, Hugh James (Thesis advisor) / Kozicki, Michael (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2015