ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
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Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Understanding charge transport in single molecules covalently bonded to electrodes is a fundamental goal in the field of molecular electronics. In the past decade, it has become possible to measure charge transport on the single-molecule level using the STM break junction method. Measurements on the single-molecule level shed light on charge transport phenomena which would otherwise be obfuscated by ensemble measurements of groups of molecules. This thesis will discuss three projects carried out using STM break junction. In the first project, the transition between two different charge transport mechanisms is reported in a set of molecular wires. The shortest wires show highly length dependent and temperature invariant conductance behavior, whereas the longer wires show weakly length dependent and temperature dependent behavior. This trend is consistent with a model whereby conduction occurs by coherent tunneling in the shortest wires and by incoherent hopping in the longer wires. Measurements are supported with calculations and the evolution of the molecular junction during the pulling process is investigated. The second project reports controlling the formation of single-molecule junctions by means of electrochemically reducing two axial-diazonium terminal groups on a molecule, thereby producing direct Au-C covalent bonds in-situ between the molecule and gold electrodes. Step length analysis shows that the molecular junction is significantly more stable, and can be pulled over a longer distance than a comparable junction created with amine anchoring bonds. The stability of the junction is explained by the calculated lower binding energy associated with the direct Au-C bond compared with the Au-N bond. Finally, the third project investigates the role that molecular conformation plays in the conductance of oligothiophene single-molecule junctions. Ethyl substituted oligothiophenes were measured and found to exhibit temperature dependent conductance and transition voltage for molecules with between two and six repeat units. While the molecule with only one repeat unit shows temperature invariant behavior. Density functional theory calculations show that at higher temperatures the oligomers with multiple repeat units assume a more planar conformation, which increases the conjugation length and decreases the effective energy barrier of the junction.
ContributorsHines, Thomas (Author) / Tao, Nongjian (Thesis advisor) / Li, Jian (Thesis advisor) / Mujica, Vladimiro (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2013
Description
Analysing and measuring of biological or biochemical processes are of utmost importance for medical, biological and biotechnological applications. Point of care diagnostic system, composing of biosensors, have promising applications for providing cheap, accurate and portable diagnosis. Owing to these expanding medical applications and advances made by semiconductor industry biosensors have seen a tremendous growth in the past few decades. Also emergence of microfluidics and non-invasive biosensing applications are other marker propellers. Analyzing biological signals using transducers is difficult due to the challenges in interfacing an electronic system to the biological environment. Detection limit, detection time, dynamic range, specificity to the analyte, sensitivity and reliability of these devices are some of the challenges in developing and integrating these devices. Significant amount of research in the field of biosensors has been focused on improving the design, fabrication process and their integration with microfluidics to address these challenges. This work presents new techniques, design and systems to improve the interface between the electronic system and the biological environment. This dissertation uses CMOS circuit design to improve the reliability of these devices. Also this work addresses the challenges in designing the electronic system used for processing the output of the transducer, which converts biological signal into electronic signal.
ContributorsShah, Sahil S (Author) / Christen, Jennifer B (Thesis advisor) / Allee, David (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2014
Description
The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
ContributorsMaurya, Satendra Kumar (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF.
ContributorsMatush, Bradley (Author) / Clark, Lawrence T (Thesis advisor) / Allee, David (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2010
Description
Advancements in technologies like the Internet of thing causes an increase in the presence of wireless transceivers. A cooperative communication between these transceivers opens a doorway for multiple novel applications. A mobile distributed transceiver architecture is a much more dynamic environment dictating the necessity of faster synchronization among the transceivers. A possibility of simultaneous synchronization in parallel with the communication will theoretically ensure a high-speed synchronization without affecting the data rate. One such system has been implemented using a Costas loop and an extension of such synchronization technique to the full-duplex model has also been addressed. The rise in spectral demand is hard to meet with the regular Time duplex and frequency duplex communication systems. A full-duplex system is theoretically expected to double the spectral efficiency. However it comes with tremendous challenges, This thesis works on one of those challenges in implementing full-duplex synchronization. A coherent full-duplex model is designed to overcome the issue of transmitter leakage modeled as injection pulling, A known solution for this effect has been used to resolve the issue and complete the coherent full-duplex model. This establishes the simultaneous synchronization and communication system.
ContributorsDhulipala, Sailesh (Author) / Zeinolabedinzadeh, Saeed (Thesis advisor) / Trichopoulos, Georgios C. (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2021
Description
This dissertation consists of four parts: design of antenna in lossy media, analysisof wire antennas using electric field integral equation (EFIE) and wavelets, modeling and measurement of grounded waveguide coplanar waveguide (GCPW) for automotive radar, and E-Band 3-D printed antenna and measurement using VNA. In the first part, the antenna is modeled and simulated in lossy media. First, the vector wave functions is solved in the fundamental mode. Next the energy flow velocity is plotted to show near-field energy distribution for both TM and TE in air and seawater environment. Finally the power relation in seawater is derived to calculate the source dipole moment and required power.
In the second part, the current distribution on the antenna is derived by solving EFIE with moment of methods (MoM). Both triangle and Coifman wavelet (Coiflet) are used as basis and weight functions. Then Input impedance of the antenna is computed and results are compared with traditional sinusoid current distribution assumption. Finally the input impedance of designed antenna is computed and matching network is designed and show resonant at designed frequency.
In the third part, GCPW is modeled and measured in E-band. Laboratory measurements are conducted in 75 to 84 GHz. The original system is embedded with error boxes due to misalignment and needed to be de-embedded. Then the measurement data is processed and the results is compared with raw data.
In the fourth part, the horn antennas and slotted waveguide array antenna (SWA) are designed for automotive radar in 75GHz to 78GHz. The horn antennas are fabricated using 3D printing of ABS material, and electro-plating with copper. The analytic solution and HFSS simulation show good agreement with measurement.
ContributorsZhou, Sai (Author) / Pan, George (Thesis advisor) / Aberle, James (Committee member) / Palais, Joseph (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2021
Description
Since the invention of the automobile, engineers have been designing and making newer and newer improvements to them in order to provide customers with safer, faster, more reliable, and more comfortable vehicles. With each new generation, new technology can be seen being introduced into mainstream products, one of which that is currently being pushed is that of autonomy. Established brand manufacturers and small research teams have been dedicated for years to find a way to make the automobile autonomous with none of them being able to confidently answer that they have found a solution. Among the engineering community there are two schools of thought when solving this issue: camera and LiDAR; some believe that only cameras and computer vision are required while other believe that LiDAR is the solution. The most optimal case is to use both cameras and LiDAR’s together in order to increase reliability and ensure data confidence. Designers are reluctant to use LiDAR systems due to their massive weight, cost, and complexity; with too many moving components, these systems are very bulky and have multiple costly, moving parts that eventually need replacement due to their constant motion. The solution to this problem is to develop a solid-state LiDAR system which would solve all those issues previously stated and this research takes it one level further and looks into a potential prototype for a solid-state camera and Lidar package. Currently no manufacturer offers a system that contains a solid-state LiDAR system and a solid-state camera with computing capabilities, all manufacturers provided either just the camera, just the Lidar, or just the computation ability. This design will also use of the shelf COTS parts in order to increase reproducibility for open-source development and to reduce total manufacturing cost. While keeping costs low, this design is also able to keep its specs and performance on par with that of a well-used commercial product, the Velodyne VL50.
ContributorsEltohamy, Gamal (Author) / Yu, Hongbin (Thesis advisor) / Goryll, Michael (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2024
Description
An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing. Spatial separation of critical nodes in the physical design of this approach mitigates multi-node charge collection (MNCC) upsets. An advanced encryption system implemented with the proposed design, compared to a previous design with non-redundant clock trees and local delay generation. The proposed approach reduces energy per operation up to 18% over an improved version of the prior approach, with negligible area impact. It can save up to 2/3rd of the power consumption and reach maximum possible frequency, when used in non-redundant mode of operation.
ContributorsGujja, Aditya (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
The space environment comprises cosmic ray particles, heavy ions and high energy electrons and protons. Microelectronic circuits used in space applications such as satellites and space stations are prone to upsets induced by these particles. With transistor dimensions shrinking due to continued scaling, terrestrial integrated circuits are also increasingly susceptible to radiation upsets. Hence radiation hardening is a requirement for microelectronic circuits used in both space and terrestrial applications.
This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
ContributorsShambhulingaiah, Sandeep (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae sun (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2015