Matching Items (488)
Description
In order to cope with the decreasing availability of symphony jobs and collegiate faculty positions, many musicians are starting to pursue less traditional career paths. Also, to combat declining audiences, musicians are exploring ways to cultivate new and enthusiastic listeners through relevant and engaging performances. Due to these challenges, many community-based chamber music ensembles have been formed throughout the United States. These groups not only focus on performing classical music, but serve the needs of their communities as well. The problem, however, is that many musicians have not learned the business skills necessary to create these career opportunities. In this document I discuss the steps ensembles must take to develop sustainable careers. I first analyze how groups build a strong foundation through getting to know their communities and creating core values. I then discuss branding and marketing so ensembles can develop a public image and learn how to publicize themselves. This is followed by an investigation of how ensembles make and organize their money. I then examine the ways groups ensure long-lasting relationships with their communities and within the ensemble. I end by presenting three case studies of professional ensembles to show how groups create and maintain successful careers. Ensembles must develop entrepreneurship skills in addition to cultivating their artistry. These business concepts are crucial to the longevity of chamber groups. Through interviews of successful ensemble members and my own personal experiences in the Tetra String Quartet, I provide a guide for musicians to use when creating a community-based ensemble.
ContributorsDalbey, Jenna (Author) / Landschoot, Thomas (Thesis advisor) / McLin, Katherine (Committee member) / Ryan, Russell (Committee member) / Solis, Theodore (Committee member) / Spring, Robert (Committee member) / Arizona State University (Publisher)
Created2013
Description
The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to develop different methodologies. At present, MEMS devices are tested using mechanical stimuli to measure the device parameters and for calibration the device. This testing is necessary since the MEMS process is not a very well controlled process unlike CMOS. This is done using an ATE and the cost of using ATE (automatic testing equipment) contribute to 30-40% of the devices final cost. This thesis proposes an architecture which can use an Electrical Signal to stimulate the MEMS device and use the data from the MEMS response in approximating the calibration coefficients efficiently. As a proof of concept, we have designed a BIST (Built-in self-test) circuit for MEMS accelerometer. The BIST has an electrical stimulus generator, Capacitance-to-voltage converter, ∑ ∆ ADC. This thesis explains in detail the design of the Electrical stimulus generator. We have also designed a technique to correlate the parameters obtained from electrical stimuli to those obtained by mechanical stimuli. This method is cost effective since the additional circuitry needed to implement BIST is less since the technique utilizes most of the existing standard readout circuitry already present.
ContributorsJangala Naga, Naveen Sai (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
Switch mode DC/DC converters are suited for battery powered applications, due to their high efficiency, which help in conserving the battery lifetime. Fixed Frequency PWM based converters, which are generally used for these applications offer good voltage regulation, low ripple and excellent efficiency at high load currents. However at light load currents, fixed frequency PWM converters suffer from poor efficiencies The PFM control offers higher efficiency at light loads at the cost of a higher ripple. The PWM has a poor efficiency at light loads but good voltage ripple characteristics, due to a high switching frequency. To get the best of both control modes, both loops are used together with the control switched from one loop to another based on the load current. Such architectures are referred to as hybrid converters. While transition from PFM to PWM loop can be made by estimating the average load current, transition from PFM to PWM requires voltage or peak current sensing. This theses implements a hysteretic PFM solution for a synchronous buck converter with external MOSFET's, to achieve efficiencies of about 80% at light loads. As the PFM loop operates independently of the PWM loop, a transition circuit for automatically transitioning from PFM to PWM is implemented. The transition circuit is implemented digitally without needing any external voltage or current sensing circuit.
ContributorsVivek, Parasuram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Increasing computational demands in data centers require facilities to operate at higher ambient temperatures and at higher power densities. Conventionally, data centers are cooled with electrically-driven vapor-compressor equipment. This paper proposes an alternative data center cooling architecture that is heat-driven. The source is heat produced by the computer equipment. This dissertation details experiments investigating the quantity and quality of heat that can be captured from a liquid-cooled microprocessor on a computer server blade from a data center. The experiments involve four liquid-cooling setups and associated heat-extraction, including a radical approach using mineral oil. The trials examine the feasibility of using the thermal energy from a CPU to drive a cooling process. Uniquely, the investigation establishes an interesting and useful relationship simultaneously among CPU temperatures, power, and utilization levels. In response to the system data, this project explores the heat, temperature and power effects of adding insulation, varying water flow, CPU loading, and varying the cold plate-to-CPU clamping pressure. The idea is to provide an optimal and steady range of temperatures necessary for a chiller to operate. Results indicate an increasing relationship among CPU temperature, power and utilization. Since the dissipated heat can be captured and removed from the system for reuse elsewhere, the need for electricity-consuming computer fans is eliminated. Thermocouple readings of CPU temperatures as high as 93°C and a calculated CPU thermal energy up to 67Wth show a sufficiently high temperature and thermal energy to serve as the input temperature and heat medium input to an absorption chiller. This dissertation performs a detailed analysis of the exergy of a processor and determines the maximum amount of energy utilizable for work. Exergy as a source of realizable work is separated into its two contributing constituents: thermal exergy and informational exergy. The informational exergy is that usable form of work contained within the most fundamental unit of information output by a switching device within a CPU. Exergetic thermal, informational and efficiency values are calculated and plotted for our particular CPU, showing how the datasheet standards compare with experimental values. The dissertation concludes with a discussion of the work's significance.
ContributorsHaywood, Anna (Author) / Phelan, Patrick E (Thesis advisor) / Herrmann, Marcus (Committee member) / Gupta, Sandeep (Committee member) / Trimble, Steve (Committee member) / Myhajlenko, Stefan (Committee member) / Arizona State University (Publisher)
Created2014
Description
Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An All-Digital Sliding-Mode (ADSM) controlled DC-DC converter, utilizing single-bit oversampled frequency domain digitizers is proposed. In the proposed approach, feedback and reference digitizing Analog-to-Digital Converters (ADC) are based on a single-bit, first order Sigma-Delta frequency to digital converter, running at 32MHz over-sampling rate. The ADSM regulator achieves 1% settling time in less than 5uSec for a load variation of 600mA. The sliding-mode controller utilizes a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady state error (or DC offset), and limits the switching frequency range, which are the two common problems associated with sliding-mode controllers. The IC is designed and fabricated on a 0.35um CMOS process occupying an active area of 2.72mm-squared. Measured peak efficiency is 83%.
ContributorsDashtestani, Ahmad (Author) / Bakkaloglu, Bertan (Thesis advisor) / Thornton, Trevor (Committee member) / Song, Hongjiang (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013
Description
Zinc oxide (ZnO), a naturally n-type semiconductor has been identified as a promising candidate to replace indium tin oxide (ITO) as the transparent electrode in solar cells, because of its wide bandgap (3.37 eV), abundant source materials and suitable refractive index (2.0 at 600 nm). Spray deposition is a convenient and low cost technique for large area and uniform deposition of semiconductor thin films. In particular, it provides an easier way to dope the film by simply adding the dopant precursor into the starting solution. In order to reduce the resistivity of undoped ZnO, many works have been done by doping in the ZnO with either group IIIA elements or VIIA elements using spray pyrolysis. However, the resistivity is still too high to meet TCO's resistivity requirement. In the present work, a novel co-spray deposition technique is developed to bypass a fundamental limitation in the conventional spray deposition technique, i.e. the deposition of metal oxides from incompatible precursors in the starting solution. With this technique, ZnO films codoped with one cationic dopant, Al, Cr, or Fe, and an anionic dopant, F, have been successfully synthesized, in which F is incompatible with all these three cationic dopants. Two starting solutions were prepared and co-sprayed through two separate spray heads. One solution contained only the F precursor, NH 4F. The second solution contained the Zn and one cationic dopant precursors, Zn(O 2CCH 3) 2 and AlCl 3, CrCl 3, or FeCl 3. The deposition was carried out at 500 °C; on soda-lime glass in air. Compared to singly-doped ZnO thin films, codoped ZnO samples showed better electrical properties. Besides, a minimum sheet resistance, 55.4 Ω/sq, was obtained for Al and F codoped ZnO films after vacuum annealing at 400 °C;, which was lower than singly-doped ZnO with either Al or F. The transmittance for the Al and F codoped ZnO samples was above 90% in the visible range. This co-spray deposition technique provides a simple and cost-effective way to synthesize metal oxides from incompatible precursors with improved properties.
ContributorsZhou, Bin (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2013
Description
Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG).
ContributorsDandamudi, Pradeep (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Holbert, Keith E. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013