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Description
The rapid growth of emerging technologies is placing enormous demand on the seamless access to the extensive amount of data, which drives an unprecedented need for substantially higher data-transfer rates. As 1.6 Terabit Ethernet (TbE) specifications are being developed, high speed interconnects along with advanced materials and processes play a crucial role in technology enabling. However, validation of interconnect performance becomes increasingly challenging at these higher speeds. High-speed interconnect behavior can be reliably predicted if interconnect models are successfully validated against measurements. In industry, it is still not common practice to perform validation at actual use conditions. Therefore, there is an urge for a restructured design methodology and metrology based on temperature and humidity, to set realistic specs for high speed interconnects and reduce probability of failure under variations. Uncertainty quantification and propagation for interconnect validation is critical to assess the correlation quality more objectively, as well as to determine the bottleneck to improve the accuracy, repeatability and reproducibility of all the measurements involved in validation. The purpose of this work is to create a methodology that is both academically rigorous and has a significant impact on industry. This methodology provides an accurate characterization of the electrical performance of interconnects under realistic use-conditions, accompanied by an uncertainty analysis to improve the assessment of correlation quality. Part of this work contributed to the Packaging Benchmark Suite developed by IEEE EPS technical committee on electrical design, modeling, and simulation.
ContributorsGeyik, Cemil S (Author) / Aberle, James T (Thesis advisor) / Zhang, Zhichao (Committee member) / Polka, Lesley A (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2023
Description
Recent advancements in communication standards, such as 5G demand transmitter hardware to support high data rates with high energy efficiency. With the revolution of communication standards, modulation schemes have become more complex and require high peak-to-average (PAPR) signals. In wireless transceiver hardware, the power amplifier (PA) consumes most of the transceiver’s DC power and is typically the bottleneck for transmitter linearity. Therefore, the transmitter’s performance directly depends on the PA. To support high PAPR signals, the PA must operate efficiently at its saturated and backoff output power. Maintaining high efficiency at both peak and backoff output power is challenging. One effective technique for addressing this problem is load modulation. Some of the prominent load-modulated PA architectures are outphasing PAs, load-modulated balanced amplifiers (LMBA), envelope elimination and restoration (EER), envelope tracking (ET), Doherty power amplifiers (DPA), and polar transmitters. Amongst them, the DPA is the most popular for infrastructure applications due to its simpler architecture compared to other techniques and linearizability with digital pre-distortion (DPD). Another crucial characteristic of progressing communication standards is wide signal bandwidths. High-efficiency power amplifiers like class J/F/F-1 and load-modulated PAs like the DPA exhibit narrowband performance because the amplifiers require precise output impedance terminations. Therefore, it is equally essential to develop adaptable PA solutions to process radio frequency (RF) signals with wide bandwidths. To support modern and future cellular infrastructure, RF PAs need to be innovated to increase the backoff power efficiency by two times or more and support ten times or more wider bandwidths than current state-of-the-art PAs. This work presents five RF PA analyses and implementations to support future wireless communications transmitter hardware. Chapter 2 presents an optimized output-matching network analysis and design to achieve extended output power backoff of the DPA. Chapters 3 and 4 unveil two bandwidth enhancement techniques for the DPA while maintaining extended output power backoff. Chapter 5 exhibits a dual-band hybrid mode PA design targeted for wideband applications. Chapter 6 presents a built-in self-test circuit integrated into a PA for output impedance monitoring. This can alleviate the PA performance degradation due to the variation in the PA's output load over frequency, process, and aging. All RF PAs in this dissertation are implemented using Gallium Nitride (GaN)-based high electron mobility transistors (HEMT), and the realized designs validate the proposed PAs' theories/architectures.
ContributorsRoychowdhury, Debatrayee (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Aberle, James (Committee member) / Arizona State University (Publisher)
Created2024
Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling
Description
The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistorlevel netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. This work aims to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on the flash ADC (Analog-to-Digital Converter), show that accurate simulations can be achieved at a fraction of the simulation time.
ContributorsModala, Nikhil Sagar (Author) / Ozev, Sule (Thesis advisor) / Chakrabarty, Krishnendu (Committee member) / Abraham, Seth (Committee member) / Arizona State University (Publisher)
Created2024
Description
Integrating analog circuits with the most advanced digitally-tuned processes increases the defect rates and the risk of in-field wear out. Coupled with the reduced accessibility arising from this level of integration, increasing defect rates necessitate systematic approaches to analog testing. Structural built-in self-test (BIST) for analog circuits can reduce test development complexity. Proposing a robust and low-cost structural BIST method for analog circuits. The proposed method relies on perturbing the analog circuit at an injection point and observing the result at an observation point as a digitally measurable time delay. Injection can be achieved via simple ON/OFF keying while the observation can be achieved by a self-referencing comparator. Multiple injection points can be selected at low cost (single transistor) while the observation circuit can be shared across many injection points and different circuit blocks.
ContributorsRaghavendra, Chinmaye (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2024
Description
This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
ContributorsBHARDWAJ, SUMIT (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation.
ContributorsGao, Hang (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2018
Description
This dissertation proposes and presents two different passive sigma-delta
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
ContributorsEROL, OSMAN EMIR (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Blain-Christen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018
Description
RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed.
In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.
In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.
ContributorsGangula, Sudheer Kumar Reddy (Author) / Kitchen, Jennifer (Thesis advisor) / Ozev, Sule (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help accelerate the hardware design process. However, depending on the target IoT application, different sensors are required to sense the signals such as heart-rate, temperature, pressure, acceleration, etc., and there is a great need for reconfigurable platforms that can prototype different sensor interfacing circuits.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
This thesis primarily focuses on two important hardware aspects of an IoT system: (a) an FPAA based reconfigurable sensing front-end system and (b) an FPGA based reconfigurable processing system. To enable reconfiguration capability for any sensor type, Programmable ANalog Device Array (PANDA), a transistor-level analog reconfigurable platform is proposed. CAD tools required for implementation of front-end circuits on the platform are also developed. To demonstrate the capability of the platform on silicon, a small-scale array of 24×25 PANDA cells is fabricated in 65nm technology. Several analog circuit building blocks including amplifiers, bias circuits and filters are prototyped on the platform, which demonstrates the effectiveness of the platform for rapid prototyping IoT sensor interfaces.
IoT systems typically use machine learning algorithms that run on the servers to process the data in order to make decisions. Recently, embedded processors are being used to preprocess the data at the energy-constrained sensor node or at IoT gateway, which saves considerable energy for transmission and bandwidth. Using conventional CPU based systems for implementing the machine learning algorithms is not energy-efficient. Hence an FPGA based hardware accelerator is proposed and an optimization methodology is developed to maximize throughput of any convolutional neural network (CNN) based machine learning algorithm on a resource-constrained FPGA.
ContributorsSuda, Naveen (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Yu, Shimeng (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016