Matching Items (62)
Description
The availability of a wide range of general purpose as well as accelerator cores on
modern smartphones means that a significant number of applications can be executed
on a smartphone simultaneously, resulting in an ever increasing demand on the memory
subsystem. While the increased computation capability is intended for improving
user experience, memory requests from each concurrent application exhibit unique
memory access patterns as well as specific timing constraints. If not considered, this
could lead to significant memory contention and result in lowered user experience.
This work first analyzes the impact of memory degradation caused by the interference
at the memory system for a broad range of commonly-used smartphone applications.
The real system characterization results show that smartphone applications,
such as web browsing and media playback, suffer significant performance degradation.
This is caused by shared resource contention at the application processor’s last-level
cache, the communication fabric, and the main memory.
Based on the detailed characterization results, rest of this thesis focuses on the
design of an effective memory interference mitigation technique. Since web browsing,
being one of the most commonly-used smartphone applications and represents many
html-based smartphone applications, my thesis focuses on meeting the performance
requirement of a web browser on a smartphone in the presence of background processes
and co-scheduled applications. My thesis proposes a light-weight user space frequency
governor to mitigate the degradation caused by interfering applications, by predicting
the performance and power consumption of web browsing. The governor selects an
optimal energy-efficient frequency setting periodically by using the statically-trained
performance and power models with dynamically-varying architecture and system
conditions, such as the memory access intensity of background processes and/or coscheduled applications, and temperature of cores. The governor has been extensively evaluated on a Nexus 5 smartphone over a diverse range of mobile workloads. By
operating at the most energy-efficient frequency setting in the presence of interference,
energy efficiency is improved by as much as 35% and with an average of 18% compared
to the existing interactive governor, while maintaining the satisfactory performance
of web page loading under 3 seconds.
modern smartphones means that a significant number of applications can be executed
on a smartphone simultaneously, resulting in an ever increasing demand on the memory
subsystem. While the increased computation capability is intended for improving
user experience, memory requests from each concurrent application exhibit unique
memory access patterns as well as specific timing constraints. If not considered, this
could lead to significant memory contention and result in lowered user experience.
This work first analyzes the impact of memory degradation caused by the interference
at the memory system for a broad range of commonly-used smartphone applications.
The real system characterization results show that smartphone applications,
such as web browsing and media playback, suffer significant performance degradation.
This is caused by shared resource contention at the application processor’s last-level
cache, the communication fabric, and the main memory.
Based on the detailed characterization results, rest of this thesis focuses on the
design of an effective memory interference mitigation technique. Since web browsing,
being one of the most commonly-used smartphone applications and represents many
html-based smartphone applications, my thesis focuses on meeting the performance
requirement of a web browser on a smartphone in the presence of background processes
and co-scheduled applications. My thesis proposes a light-weight user space frequency
governor to mitigate the degradation caused by interfering applications, by predicting
the performance and power consumption of web browsing. The governor selects an
optimal energy-efficient frequency setting periodically by using the statically-trained
performance and power models with dynamically-varying architecture and system
conditions, such as the memory access intensity of background processes and/or coscheduled applications, and temperature of cores. The governor has been extensively evaluated on a Nexus 5 smartphone over a diverse range of mobile workloads. By
operating at the most energy-efficient frequency setting in the presence of interference,
energy efficiency is improved by as much as 35% and with an average of 18% compared
to the existing interactive governor, while maintaining the satisfactory performance
of web page loading under 3 seconds.
ContributorsShingari, Davesh (Author) / Wu, Carole-Jean (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2016
Description
Vision is the ability to see and interpret any visual stimulus. It is one of the most fundamental and complex tasks the brain performs. Its complexity can be understood from the fact that close to 50% of the human brain is dedicated to vision. The brain receives an overwhelming amount of sensory information from the retina – estimated at up to 100 Mbps per optic nerve. Parallel processing of the entire visual field in real time is likely impossible for even the most sophisticated brains due to the high computational complexity of the task [1]. Yet, organisms can efficiently process this information to parse complex scenes in real time. This amazing feat of nature relies on selective attention which allows the brain to filter sensory information to select only a small subset of it for further processing.
Today, Computer Vision has become ubiquitous in our society with several in image understanding, medicine, drones, self-driving cars and many more. With the advent of GPUs and the availability of huge datasets like ImageNet, Convolutional Neural Networks (CNNs) have come to play a very important role in solving computer vision tasks, e.g object detection. However, the size of the networks become
prohibitive when higher accuracies are needed, which in turn demands more hardware. This hinders the application of CNNs to mobile platforms and stops them from hitting the real-time mark. The computational efficiency of a computer vision task, like object detection, can be enhanced by adopting a selective attention mechanism into the algorithm. In this work, this idea is explored by using Visual Proto Object Saliency algorithm [1] to crop out the areas of an image without relevant objects before a computationally intensive network like the Faster R-CNN [2] processes it.
Today, Computer Vision has become ubiquitous in our society with several in image understanding, medicine, drones, self-driving cars and many more. With the advent of GPUs and the availability of huge datasets like ImageNet, Convolutional Neural Networks (CNNs) have come to play a very important role in solving computer vision tasks, e.g object detection. However, the size of the networks become
prohibitive when higher accuracies are needed, which in turn demands more hardware. This hinders the application of CNNs to mobile platforms and stops them from hitting the real-time mark. The computational efficiency of a computer vision task, like object detection, can be enhanced by adopting a selective attention mechanism into the algorithm. In this work, this idea is explored by using Visual Proto Object Saliency algorithm [1] to crop out the areas of an image without relevant objects before a computationally intensive network like the Faster R-CNN [2] processes it.
ContributorsGorthy, Sai Rama Srivatsava (Author) / Cao, Yu (Thesis advisor) / Seo, Jae-Sun (Committee member) / Vrudhula, Sarma (Committee member) / Arizona State University (Publisher)
Created2017
Description
Fiddlevent is an event searching website written in Ruby on Rails. Fiddlevent enables any person to go online and find local events that interest him. Fiddlevent also enables merchants to post their events online. Fiddlevent explores all challenges of website development, such as project management, database design, user interface design, deployment and the software development lifecycle. Fiddlevent aims to utilize best practices for website and software development.
ContributorsThornton, Christopher Gordon (Author) / Balasooriya, Janaka (Thesis director) / Nakamura, Mutsumi (Committee member) / Hurst, Charles (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor)
Created2013-05
ContributorsShah, Beejal (Author) / Nakamura, Mutsumi (Thesis director) / Balasooriya, Janaka (Committee member) / Wilkerson, Kelly (Committee member) / Ira A. Fulton School of Engineering (Contributor) / Barrett, The Honors College (Contributor)
Created2012-12
Description
Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing improvements by condensing simple logic gates into more complex primitives, effectively reducing gate count, pipeline depth, and number of interconnects. This work proposes a new physical implementation of threshold logic, the threshold logic latch (TLL), which overcomes the difficulties observed in previous work, particularly with respect to gate reliability in the presence of noise and process variations. Simple but effective models were created to assess the delay, power, and noise margin of TLL gates for the purpose of determining the physical parameters and assignment of input signals that achieves the lowest delay subject to constraints on power and reliability. From these models, an optimized library of standard TLL cells was developed to supplement a commercial library of static CMOS gates. The new cells were then demonstrated on a number of automatically synthesized, placed, and routed designs. A two-stage 2's complement integer multiplier designed with CMOS and TLL gates utilized 19.5% less area, 28.0% less active power, and 61.5% less leakage power than an equivalent design with the same performance using only static CMOS gates. Additionally, a two-stage 32-instruction 4-way issue queue designed with CMOS and TLL gates utilized 30.6% less area, 31.0% less active power, and 58.9% less leakage power than an equivalent design with the same performance using only static CMOS gates.
ContributorsLeshner, Samuel (Author) / Vrudhula, Sarma (Thesis advisor) / Chatha, Karamvir (Committee member) / Clark, Lawrence (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2010
Description
It is important for organizations and businesses to have some kind of online presence, as there are enormous benefits, including utilizing the power of web languages to provide services for people. However, creating a website is difficult, and often expensive. While successful businesses can use their profits to develop a costly website, organizations are not so lucky and can't afford to pay large amounts of money for theirs. Thus, the goal of this project was to provide a complete website to the Card Trick Quilters organization found in Show Low, Arizona. The website serves as both a learning experience, to see exactly what it takes to construct a website from the ground up, and a service project that will provide the Card Trick Quilters with a website that performs various services for its members, with functionality that is completely unique to the Arizona quilting community at large. The creation of the website required learning several different skills in regards to web design, such as databases, scripting languages, and even elements of graphic design. The uniqueness of the website comes from the creation of an online submission form for the annual quilt show hosted by the quilters, and an email reminder system where members of the community can submit their addresses and receive emails when there is an upcoming meeting. While there will no doubt be changes and improvements to the website in the future, the website is currently live and ready for the community to use.
ContributorsSchwarting, Jessa Lynn (Author) / Balasooriya, Janaka (Thesis director) / Nakamura, Mutsumi (Committee member) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor) / School of Computing, Informatics, and Decision Systems Engineering (Contributor)
Created2016-05
Description
As smart home devices become more common in households across the globe, it is<br/>surprising that companies who specialize in IoT devices have not exploited the world of swimming<br/>pools. As a pool owner and avid IoT user, it has become increasingly obvious to me that such<br/>devices are necessary. Thus, I have developed an embedded system – connected to a web-based<br/>reporting system – that accurately reports common chemical levels of a swimming pool. In<br/>addition, this system includes an autofill function with information about the amount of water<br/>dispensed. This system gives pool owners access to an all-in-one device that can be used on any<br/>pool, new or old. Future implementations include a personalized application to display the pool<br/>levels and user-defined suggestions when certain levels become too high or low.
ContributorsSveom, Jeremy Dale (Author) / Meuth, Ryan (Thesis director) / Vrudhula, Sarma (Committee member) / Computer Science and Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
My proposed project is an educational application that will seek to simplify the<br/>process of internalizing the chord symbols most commonly seen by those learning<br/>musical improvisation. The application will operate like a game, encouraging the<br/>user to identify chord tones within time limits and award points for successfully<br/>doing so.
ContributorsOwens, Kevin Bradyn (Author) / Balasooriya, Janaka (Thesis director) / Nakamura, Mutsumi (Committee member) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Deep neural network-based methods have been proved to achieve outstanding performance on object detection and classification tasks. Deep neural networks follow the ``deeper model with deeper confidence'' belief to gain a higher recognition accuracy. However, reducing these networks' computational costs remains a challenge, which impedes their deployment on embedded devices. For instance, the intersection management of Connected Autonomous Vehicles (CAVs) requires running computationally intensive object recognition algorithms on low-power traffic cameras. This dissertation aims to study the effect of a dynamic hardware and software approach to address this issue. Characteristics of real-world applications can facilitate this dynamic adjustment and reduce the computation. Specifically, this dissertation starts with a dynamic hardware approach that adjusts itself based on the toughness of input and extracts deeper features if needed. Next, an adaptive learning mechanism has been studied that use extracted feature from previous inputs to improve system performance. Finally, a system (ARGOS) was proposed and evaluated that can be run on embedded systems while maintaining the desired accuracy. This system adopts shallow features at inference time, but it can switch to deep features if the system desires a higher accuracy. To improve the performance, ARGOS distills the temporal knowledge from deep features to the shallow system. Moreover, ARGOS reduces the computation furthermore by focusing on regions of interest. The response time and mean average precision are adopted for the performance evaluation to evaluate the proposed ARGOS system.
ContributorsFarhadi, Mohammad (Author) / Yang, Yezhou (Thesis advisor) / Vrudhula, Sarma (Committee member) / Wu, Carole-Jean (Committee member) / Ren, Yi (Committee member) / Arizona State University (Publisher)
Created2022
Description
Brushless DC (BLDC) motors are becoming increasingly common in various industrial and commercial applications such as micromobility and robotics due to their high torque density and efficiency. A BLDC Motor is a three-phase synchronous motor that is very similar to a non-salient Permanent Magnet Synchronous Motor (PMSM) with key differences lying in the non-ideal characteristics of the motor; the most prominent of these is BLDC motors have trapezoidal-shaped Back-Electromotive Force (BEMF). Despite their advantages, a present weakness of BLDC motors is the difficulty controlling these motors at standstill and low-speed conditions that require high torque. These operating conditions are common in the target applications and almost always necessitate the use of external sensors which introduce additional costs and points of failure. As such, sensorless based methods of position estimation would serve to improve system reliability, cost, and efficiency. High Frequency (HF) pulsating voltage injection in the direct axis is a popular method of sensorless control of salient-pole Interior-mount Permanent Magnet Synchronous Motors (IPMSM); however, existing methods are not sufficiently robust for use in BLDC and small Surface-mount Permanent Magnet Synchronous Motors (SPMSM) and are accompanied by other issues, such as acoustic noise. This thesis proposes novel improvements to the method of High Frequency Voltage Injection to allow for practical use in BLDC Motors and small SPMSM. Proposed improvements include 1) a hybrid frequency generator which allows for dynamic frequency scaling to improve tracking and eliminate acoustic noise, 2) robust error calculation that is stable despite the non-ideal characteristics of BLDC Motors, 3) gain engineering of Proportional-Integral (PI) type Phase-Locked-Loop (PLL) trackers that further lend stability, 4) observer decoupling mechanism to allow for seamless transition into state-of-the-art BEMF sensing methods at high speed, and 5) saliency boosting that allows for continuous tracking of saliency under high torque load. Experimental tests with a quadrature encoder and torque efficiency calculations on a dynamometer verify the practicality of the proposed algorithm and improvements.
ContributorsYin, Kai (Author) / Vrudhula, Sarma (Thesis advisor) / Chickamenahalli, Shamala (Thesis advisor) / Pal, Anamitra (Committee member) / Arizona State University (Publisher)
Created2021