Matching Items (17)
Description
This PhD thesis consists of three main themes. The first part focusses on modeling of Silver (Ag)-Chalcogenide glass based resistive memory devices known as the Programmable Metallization Cell (PMC). The proposed models are examined with the Technology Computer Aided Design (TCAD) simulations. In order to find a relationship between electrochemistry and carrier-trap statistics in chalcogenide glass films, an analytical mapping for electron trapping is derived. Then, a physical-based model is proposed in order to explain the dynamic behavior of the photodoping mechanism in lateral PMCs. At the end, in order to extract the time constant of ChG materials, a method which enables us to determine the carriers’ mobility with and without the UV light exposure is proposed. In order to validate these models, the results of TCAD simulations using Silvaco ATLAS are also presented in the study, which show good agreement.
In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized.
The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond.
In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized.
The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond.
ContributorsSaremi, Mehdi (Author) / Goodnick, Stephen M (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael N (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2017
Description
The Programmable Metallization Cell (PMC) is a novel solid-state resistive switching technology. It has a simple metal-insulator-metal “MIM” structure with one metal being electrochemically active (Cu) and the other one being inert (Pt or W), an insulating film (silica) acts as solid electrolyte for ion transport is sandwiched between these two electrodes. PMC’s resistance can be altered by an external electrical stimulus. The change of resistance is attributed to the formation or dissolution of Cu metal filament(s) within the silica layer which is associated with electrochemical redox reactions and ion transportation. In this dissertation, a comprehensive study of microfabrication method and its impacts on performance of PMC device is demonstrated, gamma-ray total ionizing dose (TID) impacts on device reliability is investigated, and the materials properties of doped/undoped silica switching layers are illuminated by impedance spectroscopy (IS). Due to the inherent CMOS compatibility, Cu-silica PMCs have great potential to be adopted in many emerging technologies, such as non-volatile storage cells and selector cells in ultra-dense 3D crosspoint memories, as well as electronic synapses in brain-inspired neuromorphic computing. Cu-silica PMC device performance for these applications is also assessed in this dissertation.
ContributorsChen, Wenhao (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Thesis advisor) / Yu, Shimeng (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2017
Description
Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of these cations. This dissertation presents electrical characterization results on Cu-SiO2 based PMC devices, which due to the na- ture of materials can be easily integrated into the current Complimentary metal oxide semiconductor (CMOS) process line. Device structures representing individual mem- ory cells based on W bottom electrode and n-type Si bottom electrode were fabricated for characterization. For the W bottom electrode based devices, switching was ob- served for voltages in the range of 500mV and current value as low as 100 nA showing the electrochemical nature and low power potential. The ON state showed a direct de- pendence on the programming current, showing the possibility of multi-bit storage in a single cell. Room temperature retention was demonstrated in excess of 105 seconds and endurance to approximately 107 cycles. Switching was observed for microsecond duration 3 V amplitude pulses. Material characterization results from Raman, X-ray diffraction, Rutherford backscattering and Secondary-ion mass spectroscopy analysis shows the influence of processing conditions on the Cu concentration within the film and also the presence of Cu as free atoms. The results seemed to indicate stress-induced void formation in the SiO2 matrix as the driving mechanism for Cu diffusion into the SiO2 film. Cu/SiO2
Si based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode.
Si based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode.
ContributorsPuthenthermadam, Sarath (Author) / Kozicki, Michael N (Thesis advisor) / Diaz, Rodolfo (Committee member) / Schroder, Dieter K. (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2011
Description
Electronic devices are gaining an increasing market share in the medical field. Medical devices are becoming more sophisticated, and encompassing more applications. Unlike consumer electronics, medical devices have far more limitations when it comes to area, power and most importantly reliability. The medical devices industry has recently seen the advantages of using Flash memory instead of Read Only Memory (ROM) for firmware storage, and in some cases to replace Electrically Programmable Read Only Memories (EEPROMs) in medical devices for frequent data storage. There are direct advantages to using Flash memory instead of Read Only Memory, most importantly the fact that firmware can be rewritten along the development cycle and in the field. However, Flash technology requires high voltage circuitry that makes it harder to integrate into low power devices. There have been a lot of advances in Non-Volatile Memory (NVM) technologies, and many Flash rivals are starting to gain attention. The purpose of this thesis is to evaluate these new technologies against Flash to determine the feasibility as well as the advantages of each technology. The focus is on embedded memory in a medical device micro-controller and application specific integrated circuits (ASIC). A behavioral model of a Programmable Metallization Cell (PMC) was used to simulate the behavior and determine the advantages of using PMC technology versus flash. When compared to flash test data, PMC based embedded memory showed a reduction in power consumption by many orders of magnitude. Analysis showed that an approximated 20% device longevity increase can be achieved by using embedded PMC technology.
ContributorsHag, Eslam E (Author) / Kozicki, Michael N (Thesis advisor) / Schroder, Dieter K. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2010
Description
This work explores the application and optimization of laser patterning of dielectrics on textured crystalline silicon for improving the performance of industrial silicon solar cells. Current direct laser patterning processes introduce defects to the surface of the solar cell as a result of the film transparency and the intensity variation of the laser induced by the textured surface. As a means of overcoming these challenges, a co-deposited protective masking film was developed that is directly patterned with laser light at greatly depreciated light intensities that allows for selective chemical etching of the underlying dielectric films without incurring substantial defects to the surface of the device. Initial defects produced by the process are carefully evaluated with electron microscopy techniques and their mechanism for generation is identified and compensated. Further, an analysis of the opening fraction within the laser spot is evaluated –the area of removed film within the laser spot divided by the area of the laser spot– and residue produced by the laser process within the contact opening is studied. Once identified, this non-damaging laser process is a promising alternative to the standard screen print and fire process currently used by industry for metallization of silicon solar cells. Smaller contacts may be made with the laser process that are as of yet unattainable with screen printing, allowing for a decrease in shading losses. Additionally, the use of patterning allows for silver-free metallization and improved conductivity in the contacts, thereby decreasing parasitic losses in the device.
ContributorsBailly, Mark (Author) / Bowden, Stuart G (Thesis advisor) / King, Richard R (Committee member) / Kozicki, Michael N (Committee member) / Holman, Zachary C (Committee member) / Arizona State University (Publisher)
Created2018
Description
ABSTRACT
Programmable metallization cell (PMC) technology uses the mechanism of metal ion transport in solid electrolytes and electrochemical redox reactions to form metallic electrodeposits. When a positive bias is applied from anode to cathode, atoms at the anode are oxidized to ions and dissolve in the solid electrolyte. They travel to the cathode under the influence of an electric field, where they are reduced to form electrodeposits. These electrodeposits are filamentary in nature and grow in different patterns. Devices that make use of the principle of filament growth have applications in memory, RF switching, and hardware security.
The solid electrolyte under investigation is tungsten trioxide with copper deposited on top. For a standard PMC, these layers are heated in a convection oven to dope the electrolyte. Once the heating process is completed, electrodes are deposited on top of the electrolyte and biased to grow the filaments. What is investigated is the rate of dendritic growth to applied field on the PMC and the composition of the electrolyte. Also investigated are modified three-terminal PMC capacitance change devices. These devices have a buried sensing electrode that senses the increasing capacitance as the filaments grow and increase the upper electrode area.
The rate of dendritic growth in the tungsten trioxide and copper electrolyte of different chemistries and applied field to the PMC devices is the important parameter. The rate of dendritic growth is related to the change of capacitance. Through sensing the change in capacitance over time the modified PMC device will function as an odometer device that can be attached to chips. The attachment of these devices to chips, help in preventing illegal recycling of old chips by marking those chips as old. This will prevent would-be attackers from inserting modified chips in systems that will enable them to by-pass any software security precautions.
Programmable metallization cell (PMC) technology uses the mechanism of metal ion transport in solid electrolytes and electrochemical redox reactions to form metallic electrodeposits. When a positive bias is applied from anode to cathode, atoms at the anode are oxidized to ions and dissolve in the solid electrolyte. They travel to the cathode under the influence of an electric field, where they are reduced to form electrodeposits. These electrodeposits are filamentary in nature and grow in different patterns. Devices that make use of the principle of filament growth have applications in memory, RF switching, and hardware security.
The solid electrolyte under investigation is tungsten trioxide with copper deposited on top. For a standard PMC, these layers are heated in a convection oven to dope the electrolyte. Once the heating process is completed, electrodes are deposited on top of the electrolyte and biased to grow the filaments. What is investigated is the rate of dendritic growth to applied field on the PMC and the composition of the electrolyte. Also investigated are modified three-terminal PMC capacitance change devices. These devices have a buried sensing electrode that senses the increasing capacitance as the filaments grow and increase the upper electrode area.
The rate of dendritic growth in the tungsten trioxide and copper electrolyte of different chemistries and applied field to the PMC devices is the important parameter. The rate of dendritic growth is related to the change of capacitance. Through sensing the change in capacitance over time the modified PMC device will function as an odometer device that can be attached to chips. The attachment of these devices to chips, help in preventing illegal recycling of old chips by marking those chips as old. This will prevent would-be attackers from inserting modified chips in systems that will enable them to by-pass any software security precautions.
ContributorsKrishnan, Anand (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Gonzalez-Velo, Yago (Committee member) / Arizona State University (Publisher)
Created2019
Description
Programmable Metallization Cell (PMC) devices are, in essence, redox-based
solid-state resistive switching devices that rely on ion transport through a solid electrolyte (SE) layer from anode to cathode. Analysis and modeling of the effect of different fabrication and processing parameter/conditions on PMC devices are crucial for future electronics. Furthermore, this work is even more significant for devices utilizing back-end- of-line (BEOL) compatible materials such as Cu, W, their oxides and SiOx as these devices offer cost effectiveness thanks to their inherent foundry-ready nature. In this dissertation, effect of annealing conditions and cathode material on the performance of Cu-SiOx vertical devices is investigated which shows that W-based devices have much lower forming voltage and initial resistance values. Also, higher annealing temperatures first lead to an increase in forming voltage from 400 °C to 500 °C, then a drastic decrease at 550 °C due to Cu island formation at the Cu/SiOx interface. Next, the characterization and modeling of the bilayer Cu2O/Cu-WO3 obtained by annealing the deposited Cu/WO3 stacks in air at BEOL-compatible temperatures is presented that display unique characteristics for lateral PMC devices. First, thin film oxidation kinetics of Cu is studied which show a parabolic relationship with annealing time and an activation energy of 0.70 eV. Grown Cu2O shows a cauliflower-like morphology where feature size on the surface increase with annealing time and temperature. Then, diffusion kinetics of Cu in WO3 is examined where the activation energy of diffusion of Cu into WO3 is calculated to be 0.74 eV. Cu was found to form clusters in the WO3 host which was revealed by imaging. Moreover, using the oxidation and diffusion analyses, a Matlab model is established for modeling the bilayer for process and annealing-condition optimization. The model is built to produce the resulting Cu2O thickness and Cu concentration in Cu-WO3. Additionally, material characterization, preliminary electrical results along with modeling of lateral PMC devices utilizing the bilayer is also demonstrated. By tuning the process parameters such as deposited Cu thickness and annealing conditions, a low-resistive Cu2O layer was achieved which dramatically enhanced the electrodeposition growth rate for lateral PMC devices.
solid-state resistive switching devices that rely on ion transport through a solid electrolyte (SE) layer from anode to cathode. Analysis and modeling of the effect of different fabrication and processing parameter/conditions on PMC devices are crucial for future electronics. Furthermore, this work is even more significant for devices utilizing back-end- of-line (BEOL) compatible materials such as Cu, W, their oxides and SiOx as these devices offer cost effectiveness thanks to their inherent foundry-ready nature. In this dissertation, effect of annealing conditions and cathode material on the performance of Cu-SiOx vertical devices is investigated which shows that W-based devices have much lower forming voltage and initial resistance values. Also, higher annealing temperatures first lead to an increase in forming voltage from 400 °C to 500 °C, then a drastic decrease at 550 °C due to Cu island formation at the Cu/SiOx interface. Next, the characterization and modeling of the bilayer Cu2O/Cu-WO3 obtained by annealing the deposited Cu/WO3 stacks in air at BEOL-compatible temperatures is presented that display unique characteristics for lateral PMC devices. First, thin film oxidation kinetics of Cu is studied which show a parabolic relationship with annealing time and an activation energy of 0.70 eV. Grown Cu2O shows a cauliflower-like morphology where feature size on the surface increase with annealing time and temperature. Then, diffusion kinetics of Cu in WO3 is examined where the activation energy of diffusion of Cu into WO3 is calculated to be 0.74 eV. Cu was found to form clusters in the WO3 host which was revealed by imaging. Moreover, using the oxidation and diffusion analyses, a Matlab model is established for modeling the bilayer for process and annealing-condition optimization. The model is built to produce the resulting Cu2O thickness and Cu concentration in Cu-WO3. Additionally, material characterization, preliminary electrical results along with modeling of lateral PMC devices utilizing the bilayer is also demonstrated. By tuning the process parameters such as deposited Cu thickness and annealing conditions, a low-resistive Cu2O layer was achieved which dramatically enhanced the electrodeposition growth rate for lateral PMC devices.
ContributorsBalaban, Mehmet Bugra (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Committee member) / Goryll, Michael (Committee member, Committee member) / Arizona State University (Publisher)
Created2020