Matching Items (135)
Description
The development of portable electronic systems has been a fundamental factor to the emergence of new applications including ubiquitous smart devices, self-driving vehicles. Power-Management Integrated Circuits (PMICs) which are a key component of such systems must maintain high efficiency and reliability for the final system to be appealing from a size and cost perspective. As technology advances, such portable systems require high output currents at low voltages from their PMICs leading to thermal reliability concerns. The reliability and power integrity of PMICs in such systems also degrades when operated in harsh environments. This dissertation presents solutions to solve two such reliability problems.The first part of this work presents a scalable, daisy-chain solution to parallelize multiple low-dropout linear (LDO) regulators to increase the total output current at low voltages. This printed circuit board (PCB) friendly approach achieves output current sharing without the need for any off-chip active or passive components or matched PCB traces thus reducing the overall system cost. Fully integrated current sensing based on dynamic element matching eliminates the need for any off-chip current sensing components. A current sharing accuracy of 2.613% and 2.789% for output voltages of 3V and 1V respectively and an output current of 2A per LDO are measured for the parallel LDO system implemented in a 0.18μm process. Thermal images demonstrate that the parallel LDO system achieves thermal equilibrium and stable reliable operation.
The remainder of the thesis deals with time-domain switching regulators for high-reliability applications. A time-domain based buck and boost controller with time as the processing variable is developed for use in harsh environments. The controller features adaptive on-time / off-time generation for quasi-constant switching frequency and a time-domain comparator to implement current-mode hysteretic control. A triple redundant bandgap reference is also developed to mitigate the effects of radiation. Measurement results are showcased for a buck and boost converter with a common controller IC implemented in a 0.18μm process and an external power stage. The converter achieves a peak efficiency of 92.22% as a buck for an output current of 5A and an output voltage of 5V. Similarly, the converter achieves an efficiency of 95.97% as a boost for an output current of 1.25A and an output voltage of 30.4V.
ContributorsTalele, Bhushan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Seo, Jae-Sun (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2021
Description
The Compact X-ray Light Source is an x-ray source at ASU that allows scientists to study the structures and dynamics of matter on an atomic scale. The radio frequency system that provides the power to accelerate electrons in the Compact X-ray Light Source must operate with a high degree of precision. This thesis measures the precision with which that system performs.
ContributorsBabic, Gregory (Author) / Graves, William (Thesis director) / Kitchen, Jennifer (Committee member) / Holl, Mark (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / Department of Physics (Contributor)
Created2022-05
Description
In this dissertation, enhanced coherent detection of terahertz (THz) radiation is presented for Silicon integrated circuits (ICs). In general THz receivers implemented in silicon technologies face a challenge due to the high noise figure (NF) of the low noise amplifier (LNA) and low conversion gain of the radio frequency (RF) mixers. Moreover, issues with implementing local oscillators (LOs) further compound these challenges, including power driving mixes, distribution networks, and overall power consumption, particularly for large-scale arrays. To address these inherent obstacles, two notable cases of enhancing THz receiver performance are presented. In the Sideband Separation Receiver (SSR) for space-borne applications is introduced. Implemented in SiGe BiCMOS technology this broadband SSR boasts a high Image Rejection Ratio (IRR) exceeding 20 dB across 220 – 320 GHz. Employing a modified Weaver architecture, optimized for simultaneous spectral line observation, it utilizes an I/Q double down-conversion, pushing the technological boundaries of silicon and enabling large-scale focal plane array (FPA) deployment in space. Notably, the use of a sub-harmonic down-conversion mixer (SHM) significantly reduces LO power generation challenges, enhancing scalability while maintaining minimal NF.
In the 4x4 FPA active THz imager, a dual-polarized patch antenna operating at 420 GHz utilizes orthogonal polarization for RF and LO signals, coupled with a coherent homodyne power detector. Realized in 0.13µm SiGe HBT technology, the power detector is co-designing with the antenna to ensure minimal crosstalk and achieving -30dB cross-polarization isolation. Illumination of the LO enhances power detector performance without on-chip routing complexities, enabling scalability to 1K pixel THz imagers. Each pixel achieves a Noise-Equivalent Power (NEP) of 1 pW/√Hz at 420 GHz, and integration with a readout and digital filter ensures high dynamic range.
Furthermore, this study explores radiation hardening techniques to mitigate single-event effects (SEEs) in high-frequency receivers operating in space. Leveraging a W-band receiver in 90 nm SiGe BiCMOS technology, matching considerations and diverse modes of operation are employed to reduce SEE susceptibility. Transient current pulse modeling, validated through TCAD simulations, demonstrates the effectiveness of proposed techniques in substantially mitigating SETs within the proposed radiation-hardened-by-design (RHBD) receiver front-end.
ContributorsAl Seragi, Ebrahim (Author) / Zeinolabedinzadeh, Saeed (Thesis advisor) / Trichopoulos, Georgios (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2024
Description
Solar photovoltaic (PV) generation has seen significant growth in 2021, with an increase of around 22% and exceeding 1000 TWh. However, this has also led to reliability and durability issues, particularly potential induced degradation (PID), which can reduce module output by up to 30%. This study uses cell- and module-level analysis to investigate the impact of superstrate, encapsulant, and substrate on PID.The influence of different substrates and encapsulants is studied using one-cell modules, showing that substrates with poor water-blocking properties can worsen PID, and encapsulants with lower volumetric resistance can conduct easily under damp conditions, enabling PID mechanisms (results show maximum degradation of 9%). Applying an anti-soiling coating on the front glass (superstrate) reduces PID by nearly 53%. Typical superstrates have sodium which accelerates the PID process, and therefore, using such coatings can lessen the PID problem.
At the module level, the study examines the influence of weakened interface adhesion strengths in traditional Glass-Backsheet (GB) and emerging Glass-Glass (GG) (primarily bifacial modules) constructions. The findings show nearly 64% more power degradation in GG modules than in GB. Moreover, the current methods for detecting PID use new modules, which can give inaccurate information instead of DH-stressed modules for PID testing, as done in this work.
A comprehensive PID susceptibility analysis for multiple fresh bifacial constructions shows significant degradation from 20 to 50% in various constructions. The presence of glass as the substrate exacerbates the PID problem due to more ionic activity available from the two glass sides. Recovery experiments are also conducted to understand the extent of the PID issue.
Overall, this study identifies, studies, and explains the impact of superstrate, substrate, and encapsulant on the underlying PID mechanisms. Various pre- and post-stress characterization tests, including light and dark current-voltage (I-V) tests, electroluminescence (EL) imaging, infrared (IR) imaging, and UV fluorescence (UVF) imaging, are used to evaluate the findings. This study is significant as it provides insights into the PID issues in solar PV systems, which can help improve their performance and reliability.
ContributorsMahmood, Farrukh ibne (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Oh, Jaewon (Committee member) / Rajadas, John (Committee member) / Arizona State University (Publisher)
Created2023
Description
The world has seen a revolution in cellular communication with the advent of 5G (fifth-generation), which enables gigabits per second data speed with low latency, massive capacity, and increased availability. These modern wireless systems improve spectrum efficiency by employing advanced modulation techniques, but result in large peak-to-average power ratios (PAPR) of the transmitted signals that degrades the efficiency of the radio-frequency power amplifiers (PAs) in the power back-off (PBO) region. Envelope tracking (ET), which is a dynamic supply control technology to realize high efficiency PAs, is a promising approach for designing transmitters for the future. Conventional voltage regulators, such as linear regulators and switching regulators, fail to simultaneously offer high speed, high efficiency, and improved linearity. Hybrid supply modulators (HSM) that combine a linear and switching regulator emerge as promising solutions to achieve an optimized tradeoff between different design parameters. Over the years, considerable development and research efforts in industry and academia have been spent on maximizing HSM performance, and a majority of the most recently developed modulators are implemented in CMOS technology and mainly targeted for handset applications. In this dissertation, the main requirements for modern HSM designs are categorized and analyzed in detail. Next, techniques to improve HSM performance are discussed. The available device technologies for HSM and PA implementations are also delineated, and implementation challenges of an integrated ET-PA system are summarized. Finally, a Current-Mode with Dynamic Hysteresis HSM is proposed, designed, and implemented. With the proposed technique, the HSM is able to track LTE signals up to 100 MHz bandwidth. Switching at a peak frequency of 40 MHz, the design is able to track a 1 Vpp sinusoidal signal with high fidelity, has an output voltage ripple around 54 mV, and achieves a peak static and dynamic efficiency of 92.2% and 82.29%, respectively, at the maximum output. The HSM is capable of delivering a maximum output power of 425 mW and occupies a small die area of 1.6mm2. Overall, the proposed HSM promises competitive performance compared to state-of-the-art works.
ContributorsBHARDWAJ, SUMIT (Author) / Kitchen, Jennifer (Thesis advisor) / Ozev, Sule (Committee member) / Bakkaloglu, Bertan (Committee member) / Singh, Shrikant (Committee member) / Arizona State University (Publisher)
Created2024
Description
Handheld devices and personal laptops are becoming compact and complex every year with a demand to have higher power density, efficiency, and fast transient response. DC-DC boost converters are used in display and haptic drivers where the output voltage needs to be boosted higher than input voltage. The load transient response and unity gain bandwidth (UGB) of DC-DC boost converters are restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. The fast feedback (FFB) path is designed to achieve low output voltage change and fast settling time with the same UGB when compared to the conventional peak current mode control (CPCM). In the proposed PFFC method, the closed loop output impedance (ZOCL) is improved by reducing the DC value and by increasing the bandwidth of ZOCL as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for VOUT=5V, VIN=2.5V-4.4V and ILOAD=10mA-1A operating at a frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by ~2.6X and the undershoot reduces by 62% to 12μs and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/μs. The PFFC approach improves the settling time by 12X to 26us and reduces the overshoot by 56% to 56mV when compared to CPCM for 1A to 10mA load step at 2A/μs. The converter achieves a peak efficiency of 95.2% at 0.5W output power with VIN=4.4V and load regulation of 9mV/A at VIN=2.5V. The line transient response at VOUT=5V, ILOAD=700mA for VIN=3V ↔ 4V which is repeated at 280μs time period is 235mV and 245mV for CPCM and PFFC respectively.
ContributorsAlevoor, Shashank (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Sanyal, Arindham (Committee member) / Beohar, Navankur (Committee member) / Arizona State University (Publisher)
Created2023
Description
Recent advancements in communication standards, such as 5G demand transmitter hardware to support high data rates with high energy efficiency. With the revolution of communication standards, modulation schemes have become more complex and require high peak-to-average (PAPR) signals. In wireless transceiver hardware, the power amplifier (PA) consumes most of the transceiver’s DC power and is typically the bottleneck for transmitter linearity. Therefore, the transmitter’s performance directly depends on the PA. To support high PAPR signals, the PA must operate efficiently at its saturated and backoff output power. Maintaining high efficiency at both peak and backoff output power is challenging. One effective technique for addressing this problem is load modulation. Some of the prominent load-modulated PA architectures are outphasing PAs, load-modulated balanced amplifiers (LMBA), envelope elimination and restoration (EER), envelope tracking (ET), Doherty power amplifiers (DPA), and polar transmitters. Amongst them, the DPA is the most popular for infrastructure applications due to its simpler architecture compared to other techniques and linearizability with digital pre-distortion (DPD). Another crucial characteristic of progressing communication standards is wide signal bandwidths. High-efficiency power amplifiers like class J/F/F-1 and load-modulated PAs like the DPA exhibit narrowband performance because the amplifiers require precise output impedance terminations. Therefore, it is equally essential to develop adaptable PA solutions to process radio frequency (RF) signals with wide bandwidths. To support modern and future cellular infrastructure, RF PAs need to be innovated to increase the backoff power efficiency by two times or more and support ten times or more wider bandwidths than current state-of-the-art PAs. This work presents five RF PA analyses and implementations to support future wireless communications transmitter hardware. Chapter 2 presents an optimized output-matching network analysis and design to achieve extended output power backoff of the DPA. Chapters 3 and 4 unveil two bandwidth enhancement techniques for the DPA while maintaining extended output power backoff. Chapter 5 exhibits a dual-band hybrid mode PA design targeted for wideband applications. Chapter 6 presents a built-in self-test circuit integrated into a PA for output impedance monitoring. This can alleviate the PA performance degradation due to the variation in the PA's output load over frequency, process, and aging. All RF PAs in this dissertation are implemented using Gallium Nitride (GaN)-based high electron mobility transistors (HEMT), and the realized designs validate the proposed PAs' theories/architectures.
ContributorsRoychowdhury, Debatrayee (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Aberle, James (Committee member) / Arizona State University (Publisher)
Created2024
Description
Integrating analog circuits with the most advanced digitally-tuned processes increases the defect rates and the risk of in-field wear out. Coupled with the reduced accessibility arising from this level of integration, increasing defect rates necessitate systematic approaches to analog testing. Structural built-in self-test (BIST) for analog circuits can reduce test development complexity. Proposing a robust and low-cost structural BIST method for analog circuits. The proposed method relies on perturbing the analog circuit at an injection point and observing the result at an observation point as a digitally measurable time delay. Injection can be achieved via simple ON/OFF keying while the observation can be achieved by a self-referencing comparator. Multiple injection points can be selected at low cost (single transistor) while the observation circuit can be shared across many injection points and different circuit blocks.
ContributorsRaghavendra, Chinmaye (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2024
Description
This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
ContributorsBHARDWAJ, SUMIT (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
This dissertation proposes and presents two different passive sigma-delta
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step
by step process designing the zoom-ADC along with a synthesis tool that can target various
design specifications are presented. The design flow does not rely on extensive knowledge
of an experienced ADC designer. Two example set of BIST ADCs have been synthesized
with different performance requirements in 65nm CMOS process. The first ADC achieves
90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW
power. Another example achieves 78.2dB SNR in 31.25µs measurement time and
consumes 63µW power. The second ADC architecture is a multi-mode, dynamically
zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating
flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the
fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)-
independent, dynamic zooming technique, employing an interpolating zooming front-end.
The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it
suitable for cellular applications including 4G radio systems. By reconfiguring the OSR,
bias current, and component parameters, optimal power consumption can be achieved for
every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an
SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW
power consumption from a 1.2 V supply.
ContributorsEROL, OSMAN EMIR (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Blain-Christen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018