Matching Items (266)
Description
While developing autonomous intelligent robots has been the goal of many research programs, a more practical application involving intelligent robots is the formation of teams consisting of both humans and robots. An example of such an application is search and rescue operations where robots commanded by humans are sent to environments too dangerous for humans. For such human-robot interaction, natural language is considered a good communication medium as it allows humans with less training about the robot's internal language to be able to command and interact with the robot. However, any natural language communication from the human needs to be translated to a formal language that the robot can understand. Similarly, before the robot can communicate (in natural language) with the human, it needs to formulate its communique in some formal language which then gets translated into natural language. In this paper, I develop a high level language for communication between humans and robots and demonstrate various aspects through a robotics simulation. These language constructs borrow some ideas from action execution languages and are grounded with respect to simulated human-robot interaction transcripts.
ContributorsLumpkin, Barry Thomas (Author) / Baral, Chitta (Thesis advisor) / Lee, Joohyung (Committee member) / Fainekos, Georgios (Committee member) / Arizona State University (Publisher)
Created2012
Description
In recent years, we have observed the prevalence of stream applications in many embedded domains. Stream programs distinguish themselves from traditional sequential programming languages through well defined independent actors, explicit data communication, and stable code/data access patterns. In order to achieve high performance and low power, scratch pad memory (SPM) has been introduced in today's embedded multicore processors. Current design frameworks for developing stream applications on SPM enhanced embedded architectures typically do not include a compiler that can perform automatic partitioning, mapping and scheduling under limited on-chip SPM capacities and memory access delays. Consequently, many designs are implemented manually, which leads to lengthy tasks and inferior designs. In this work, optimization techniques that automatically compile stream programs onto embedded multi-core architectures are proposed. As an initial case study, we implemented an automatic target recognition (ATR) algorithm on the IBM Cell Broadband Engine (BE). Then integer linear programming (ILP) and heuristic approaches were proposed to schedule stream programs on a single core embedded processor that has an SPM with code overlay. Later, ILP and heuristic approaches for Compiling Stream programs on SPM enhanced Multicore Processors (CSMP) were studied. The proposed CSMP ILP and heuristic approaches do not optimize for cycles in stream applications. Further, the number of software pipeline stages in the implementation is dependent on actor to processing engine (PE) mapping and is uncontrollable. We next presented a Retiming technique for Throughput optimization on Embedded Multi-core processors (RTEM). RTEM approach inherently handles cycles and can accept an upper bound on the number of software pipeline stages to be generated. We further enhanced RTEM by incorporating unrolling (URSTEM) that preserves all the beneficial properties of RTEM heuristic and also scales with the number of PEs through unrolling.
ContributorsChe, Weijia (Author) / Chatha, Karam Singh (Thesis advisor) / Vrudhula, Sarma (Committee member) / Chakrabarti, Chaitali (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2012
Description
The central goal of this thesis is to develop a practical approach to validating the correctness of SSA forms. Since achieving this goal is very involved for a general program, we restrict our attention to simple programs. In particular, the programs we consider are loop-free and are comprised of simple assignments to scalar variables, as well as input and output statements. Even for such a simple program, a full formal treatment would be very involved, extending beyond the scope of an undergraduate honors thesis.
ContributorsLusi, Dylan Patrick (Author) / Bazzi, Rida (Thesis director) / Fainekos, Georgios (Committee member) / Barrett, The Honors College (Contributor) / School of Mathematical and Statistical Sciences (Contributor) / Computer Science and Engineering Program (Contributor)
Created2015-05
Description
Dynamic languages like Java enjoy robust and powerful testing tools like JUnit and Cobertura. On the other hand, while there is no shortage of unit testing frameworks for C, the nature of C makes it difficult to make frameworks as powerful as those for other languages. In this paper, we describe ZTest, a testing framework that addresses some of these shortcomings in the C unit testing landscape. We also discuss results of its application to a medium-sized C project.
ContributorsIadicicco, Alexander (Author) / Bazzi, Rida (Thesis director) / Shrivastava, Aviral (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor)
Created2015-05
Description
Utilizing an urban canopy model (UCM) developed by Zhihua Wang, Ph.D. for a research study conducted for the National Asphalt Pavement Association (NAPA), several scenarios were run in order to determine the impact on the mitigation of the urban heat island (UHI) effect. These scenarios included various roof albedo, wall albedo, ground albedo, a combination of all three albedos, roof emissivity, wall emissivity, ground emissivity, a combination of all three emissivities, and normalized building height as independent variables. Dependent variables included canyon air temperature, effective ground temperature, effective roof temperature, effective wall temperature, and sensible heat flux. It was found that emissivity does play a part in reducing the different dependent variables; however, typically emissivity values are already within a preferred range that not much can be done with them. Normalized building height has a minor impact but the impact that it does have upon the different variables is lessened with lower values of the normalized building height. Increasing the wall albedo decreased the canyon air temperature and the effective wall temperature the most compared to the other variables when considering expenses. An increase in roof albedo reduced effective roof temperature and sensible heat flux the most when taking into consideration the cost of changing the albedo of the surface. Larger values of ground albedo helped to reduce the effective ground temperature more than the other variables considered when a budget is necessary.
ContributorsHousenga, Hannah Eileen (Author) / Kaloush, Kamil (Thesis director) / Wang, Zhihua (Committee member) / Civil, Environmental and Sustainable Engineering Programs (Contributor) / Barrett, The Honors College (Contributor)
Created2015-05
Description
In this investigation, copper slag was used as a coarse aggregate in four different mixes of concrete, consisting of 0%, 25%, 50%, and 100% copper slag by volume. Locally available Salt river aggregate was used as a control, and mixes were tested for density, strength, thermal conductivity, specific heat capacity, and thermal diffusivity. Density was shown to increase with increasing copper slag content, increasing an average of 2298 kg/m^3, 2522 kg/m^3, and 2652 kg/m^3 in the 25%, 50%, and 100% mixes. This represents a 15% increase in density from 0% to 100%. Compressive strength testing indicated that the presence of copper slag in concrete provides no definitive strength benefit over Salt River aggregate. This result was expected, as concrete's strength is primarily derived from the cement matrix and not the aggregate. Thermal conductivity showed a decreasing trend with increasing copper slag content. Th control mix had an average conductivity of 0.660 W/m*K, and the 25%, 50%, and 100% mixes had conductivities of 0.649 W/m*K, 0.647 W/m*K, and 0.519 W/m*K, respectively. This represents 21% drop in thermal conductivity over the control. This result was also expected, as materials formed at higher temperatures, like copper slag, tend to have lower thermal conductivities. Specific heat capacity testing yielded results that were statistically indeterminate, though unlike strength testing this arose from inaccurate assumptions made during testing. This also prevented accurate thermal diffusivity results, as diffusivity is a function of density, thermal conductivity, and specific heat capacity. However, given the trends of the first two parameters, it is plausible to say that diffusivity in copper slag concrete would be lower than that of the control ix. All of these results were plugged into ASU's Pavement Temperature Model to see what effect they had in mitigating the UHI effect.
ContributorsLaughlin, Colin (Author) / Kaloush, Kamil (Thesis director) / Phelan, Patrick (Committee member) / Witczak, Kenneth (Committee member) / Barrett, The Honors College (Contributor)
Created2012-05
Description
Rapid urbanization of the planet is occurring at an unprecedented pace, primarily in arid and semi-arid hot climates [Golden, J.S., 2004. The built environment induced urban heat island effect in rapidly urbanizing arid regions – a sustainable urban engineering complexity. Environ. Sci. J. Integr. Environ. Res. 1 (4), 321–349]. This growth has manifested itself as a cause of various impacts including elevated urban temperatures in comparison to rural sites known as the Urban Heat Island (UHI) effect [Oke, T.R., 1982. The energetic basis of the urban heat island. Q. J. R. Meteor. Soc. 108, 1–24]. Related are the increased demands for electric power as a result of population growth and increased need for mechanical cooling due to the UHI. In the United States, the Environmental Protection Agency has developed a three-prong approach of (1) cool pavements, (2) urban forestry and (3) cool roofs to mitigate the UHI. Researchers undertook an examination of micro scale benefits of the utilization of photovoltaic panels to reduce the thermal impacts to surface temperatures of pavements in comparison to urban forestry. The results of the research indicate that photovoltaic panels provide a greater thermal reduction benefit during the diurnal cycle in comparison to urban forestry while also providing the additional benefits of supporting peak energy demand, conserving water resources and utilizing a renewable energy source.
ContributorsGolden, Jay S. (Author) / Carlson, Joby (Author) / Kaloush, Kamil (Author) / Phelan, Patrick (Author)
Created2006-12-26
Description
Engineered pavements cover a large fraction of cities and offer significant potential for urban heat island mitigation. Though rapidly increasing research efforts have been devoted to the study of pavement materials, thermal interactions between buildings and the ambient environment are mostly neglected. In this study, numerical models featuring a realistic representation of building-environment thermal interactions, were applied to quantify the effect of pavements on the urban thermal environment at multiple scales. It was found that performance of pavements inside the canyon was largely determined by the canyon geometry. In a high-density residential area, modifying pavements had insignificant effect on the wall temperature and building energy consumption. At a regional scale, various pavement types were also found to have a limited cooling effect on land surface temperature and 2-m air temperature for metropolitan Phoenix. In the context of global climate change, the effect of pavement was evaluated in terms of the equivalent CO2 emission. Equivalent CO2 emission offset by reflective pavements in urban canyons was only about 13.9e46.6% of that without building canopies, depending on the canyon geometry. This study revealed the importance of building-environment thermal interactions in determining thermal conditions inside the urban canopy.
ContributorsYang, Jiachuan (Author) / Wang, Zhi-Hua (Author) / Kaloush, Kamil (Author) / Dylla, Heather (Author)
Created2016-08-22
Description
The ubiquity of embedded computational systems has exploded in recent years impacting everything from hand-held computers and automotive driver assistance to battlefield command and control and autonomous systems. Typical embedded computing systems are characterized by highly resource constrained operating environments. In particular, limited energy resources constrain performance in embedded systems often reliant on independent fuel or battery supplies. Ultimately, mitigating energy consumption without sacrificing performance in these systems is paramount. In this work power/performance optimization emphasizing prevailing data centric applications including video and signal processing is addressed for energy constrained embedded systems. Frameworks are presented which exchange quality of service (QoS) for reduced power consumption enabling power aware energy management. Power aware systems provide users with tools for precisely managing available energy resources in light of user priorities, extending availability when QoS can be sacrificed. Specifically, power aware management tools for next generation bistable electrophoretic displays and the state of the art H.264 video codec are introduced. The multiprocessor system on chip (MPSoC) paradigm is examined in the context of next generation many-core hand-held computing devices. MPSoC architectures promise to breach the power/performance wall prohibiting advancement of complex high performance single core architectures. Several many-core distributed memory MPSoC architectures are commercially available, while the tools necessary to effectively tap their enormous potential remain largely open for discovery. Adaptable scalability in many-core systems is addressed through a scalable high performance multicore H.264 video decoder implemented on the representative Cell Broadband Engine (CBE) architecture. The resulting agile performance scalable system enables efficient adaptive power optimization via decoding-rate driven sleep and voltage/frequency state management. The significant problem of mapping applications onto these architectures is additionally addressed from the perspective of instruction mapping for limited distributed memory architectures with a code overlay generator implemented on the CBE. Finally runtime scheduling and mapping of scalable applications in multitasking environments is addressed through the introduction of a lightweight work partitioning framework targeting streaming applications with low latency and near optimal throughput demonstrated on the CBE.
ContributorsBaker, Michael (Author) / Chatha, Karam S. (Thesis advisor) / Raupp, Gregory B. (Committee member) / Vrudhula, Sarma B. K. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2011
Description
Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing improvements by condensing simple logic gates into more complex primitives, effectively reducing gate count, pipeline depth, and number of interconnects. This work proposes a new physical implementation of threshold logic, the threshold logic latch (TLL), which overcomes the difficulties observed in previous work, particularly with respect to gate reliability in the presence of noise and process variations. Simple but effective models were created to assess the delay, power, and noise margin of TLL gates for the purpose of determining the physical parameters and assignment of input signals that achieves the lowest delay subject to constraints on power and reliability. From these models, an optimized library of standard TLL cells was developed to supplement a commercial library of static CMOS gates. The new cells were then demonstrated on a number of automatically synthesized, placed, and routed designs. A two-stage 2's complement integer multiplier designed with CMOS and TLL gates utilized 19.5% less area, 28.0% less active power, and 61.5% less leakage power than an equivalent design with the same performance using only static CMOS gates. Additionally, a two-stage 32-instruction 4-way issue queue designed with CMOS and TLL gates utilized 30.6% less area, 31.0% less active power, and 58.9% less leakage power than an equivalent design with the same performance using only static CMOS gates.
ContributorsLeshner, Samuel (Author) / Vrudhula, Sarma (Thesis advisor) / Chatha, Karamvir (Committee member) / Clark, Lawrence (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2010