Matching Items (107)
Description
A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA
ContributorsNaqvi, Syed Roomi (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chae, Junseok (Committee member) / Barnby, Hugh (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2011
Description
This thesis describes a synthetic task environment, CyberCog, created for the purposes of 1) understanding and measuring individual and team situation awareness in the context of a cyber security defense task and 2) providing a context for evaluating algorithms, visualizations, and other interventions that are intended to improve cyber situation awareness. CyberCog provides an interactive environment for conducting human-in-loop experiments in which the participants of the experiment perform the tasks of a cyber security defense analyst in response to a cyber-attack scenario. CyberCog generates the necessary performance measures and interaction logs needed for measuring individual and team cyber situation awareness. Moreover, the CyberCog environment provides good experimental control for conducting effective situation awareness studies while retaining realism in the scenario and in the tasks performed.
ContributorsRajivan, Prashanth (Author) / Femiani, John (Thesis advisor) / Cooke, Nancy J. (Thesis advisor) / Lindquist, Timothy (Committee member) / Gary, Kevin (Committee member) / Arizona State University (Publisher)
Created2011
Description
Intuitive decision making refers to decision making based on situational pattern recognition, which happens without deliberation. It is a fast and effortless process that occurs without complete awareness. Moreover, it is believed that implicit learning is one means by which a foundation for intuitive decision making is developed. Accordingly, the present study investigated several factors that affect implicit learning and the development of intuitive decision making in a simulated real-world environment: (1) simple versus complex situational patterns; (2) the diversity of the patterns to which an individual is exposed; (3) the underlying mechanisms. The results showed that simple patterns led to higher levels of implicit learning and intuitive decision-making accuracy than complex patterns; increased diversity enhanced implicit learning and intuitive decision-making accuracy; and an embodied mechanism, labeling, contributes to the development of intuitive decision making in a simulated real-world environment. The results suggest that simulated real-world environments can provide the basis for training intuitive decision making, that diversity is influential in the process of training intuitive decision making, and that labeling contributes to the development of intuitive decision making. These results are interpreted in the context of applied situations such as military applications involving remotely piloted aircraft.
ContributorsCovas-Smith, Christine Marie (Author) / Cooke, Nancy J. (Thesis advisor) / Patterson, Robert (Committee member) / Glenberg, Arthur (Committee member) / Homa, Donald (Committee member) / Arizona State University (Publisher)
Created2011
Description
Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA to 200mA for the direct current reading topology and from 1mA to 500mA for the indirect current reading topology across a typical board Cu-trace resistance of 1 ohm with less than 10 µV input-referred offset, 0.3 µV/°C offset drift and 0.1% accuracy for both topologies. Proposed systems avoid using a costly zero-temperature coefficient (TC) sense resistor that is normally used in typical CSM systems. Instead, both of the designs used existing Cu-trace on the printed circuit board (PCB) in place of the costly resistor. The systems use chopper stabilization at the front-end amplifier signal path to suppress input-referred offset down to less than 10 µV. Switching current-mode (SI) FIR filtering technique is used at the instrumentation amplifier output to filter out the chopping ripple caused by input offset and flicker noise by averaging half of the phase 1 signal and the other half of the phase 2 signal. In addition, residual offset mainly caused by clock feed-through and charge injection of the chopper switches at the chopping frequency and its multiple frequencies notched out by the since response of the SI-FIR filter. A frequency domain Sigma Delta ADC which is used for the indirect current reading type design enables a digital interface to processor applications with minimally added circuitries to build a simple 1st order Sigma Delta ADC. The CSMs are fabricated on a 0.7µm CMOS process with 3 levels of metal, with maximum Vds tolerance of 8V and operates across a common mode range of 0 to 26V for the direct current reading type and of 0 to 30V for the indirect current reading type achieving less than 10nV/sqrtHz of flicker noise at 100 Hz for both approaches. By using a semi-digital SI-FIR filter, residual chopper offset is suppressed down to 0.5mVpp from a baseline of 8mVpp, which is equivalent to 25dB suppression.
ContributorsYeom, Hyunsoo (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2011
Description
The objective of this project was to evaluate human factors based cognitive aids on endoscope reprocessing. The project stems from recent failures in reprocessing (cleaning) endoscopes, contributing to the spread of harmful bacterial and viral agents between patients. Three themes were found to represent a majority of problems: 1) lack of visibility (parts and tools were difficult to identify), 2) high memory demands, and 3) insufficient user feedback. In an effort to improve completion rate and eliminate error, cognitive aids were designed utilizing human factors principles that would replace existing manufacturer visual aids. Then, a usability test was conducted, which compared the endoscope reprocessing performance of novices using the standard manufacturer-provided visual aids and the new cognitive aids. Participants successfully completed 87.1% of the reprocessing procedure in the experimental condition with the use of the cognitive aids, compared to 46.3% in the control condition using only existing support materials. Twenty-five of sixty subtasks showed significant improvement in completion rates. When given a cognitive aid designed with human factors principles, participants were able to more successfully complete the reprocessing task. This resulted in an endoscope that was more likely to be safe for patient use.
ContributorsJolly, Jonathan D (Author) / Branaghan, Russell J (Thesis advisor) / Cooke, Nancy J. (Committee member) / Sanchez, Christopher (Committee member) / Arizona State University (Publisher)
Created2011
Description
Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.
ContributorsMahadevan, Rupa (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kiaei, Sayfe (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Voltage Control Oscillator (VCO) is one of the most critical blocks in Phase Lock Loops (PLLs). LC-tank VCOs have a superior phase noise performance, however they require bulky passive resonators and often calibration architectures to overcome their limited tuning range. Ring oscillator (RO) based VCOs are attractive for digital technology applications owing to their ease of integration, small die area and scalability in deep submicron processes. However, due to their supply sensitivity and poor phase noise performance, they have limited use in applications demanding low phase noise floor, such as wireless or optical transceivers. Particularly, out-of-band phase noise of RO-based PLLs is dominated by RO performance, which cannot be suppressed by the loop gain, impairing RF receiver's sensitivity or BER of optical clock-data recovery circuits. Wide loop bandwidth PLLs can overcome RO noise penalty, however, they suffer from increased in-band noise due to reference clock, phase-detector and charge-pump. The RO phase noise is determined by the noise coming from active devices, supply, ground and substrate. The authors adopt an auxiliary circuit with inverse delay sensitivity to supply noise, which compensates for the delay variation of inverter cells. Feed-forward noise-cancelling architecture that improves phase noise characteristic of RO based PLLs is presented. The proposed circuit dynamically attenuates RO phase noise contribution outside the PLL bandwidth, or in a preferred band. The implemented noise-cancelling loop potentially enables application of RO based PLL for demanding frequency synthesizers applications, such as optical links or high-speed serial I/Os.
ContributorsMin, Seungkee (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Towe, Bruce (Committee member) / Arizona State University (Publisher)
Created2011
Description
The wood-framing trade has not sufficiently been investigated to understand the work task sequencing and coordination among crew members. A new mental framework for a performing crew was developed and tested through four case studies. This framework ensured similar team performance as the one provided by task micro-scheduling in planning software. It also allowed evaluation of the effect of individual coordination within the crew on the crew's productivity. Using design information, a list of micro-activities/tasks and their predecessors was automatically generated for each piece of lumber in the four wood frames. The task precedence was generated by applying elementary geometrical and technological reasoning to each frame. Then, the duration of each task was determined based on observations from videotaped activities. Primavera's (P6) resource leveling rules were used to calculate the sequencing of tasks and the minimum duration of the whole activity for various crew sizes. The results showed quick convergence towards the minimum production time and allowed to use information from Building Information Models (BIM) to automatically establish the optimal crew sizes for frames. Late Start (LS) leveling priority rule gave the shortest duration in every case. However, the logic of LS tasks rule is too complex to be conveyed to the framing crew. Therefore, the new mental framework of a well performing framer was developed and tested to ensure high coordination. This mental framework, based on five simple rules, can be easily taught to the crew and ensures a crew productivity congruent with the one provided by the LS logic. The case studies indicate that once the worst framer in the crew surpasses the limit of 11% deviation from applying the said five rules, every additional percent of deviation reduces the productivity of the whole crew by about 4%.
ContributorsMaghiar, Marcel M (Author) / Wiezel, Avi (Thesis advisor) / Mitropoulos, Panagiotis (Committee member) / Cooke, Nancy J. (Committee member) / Arizona State University (Publisher)
Created2011