Matching Items (63)
Description
This thesis presents a power harvesting system combining energy from sub-cells of
multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost
converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current
regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A
modified hill-climbing algorithm is implemented to achieve maximum power point
tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V
output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of
65mW. Measured results show that the peak efficiency achieved is around 85%. The
power switches and control circuits are implemented in standard 0.18um CMOS process.
multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost
converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current
regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A
modified hill-climbing algorithm is implemented to achieve maximum power point
tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V
output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of
65mW. Measured results show that the peak efficiency achieved is around 85%. The
power switches and control circuits are implemented in standard 0.18um CMOS process.
ContributorsPeng, Qirong (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC).
Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners.
Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM.
Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners.
Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM.
ContributorsMedapuram, Sai Bharadwaj (Author) / Clark, Lawrence T (Thesis advisor) / Allee, David R. (Committee member) / Brunhaver, John S (Committee member) / Arizona State University (Publisher)
Created2017
Description
Accessibility to the internal nodes of an analog/mixed-signal circuit while testing is extremely difficult. Furthermore, with technology scaling, the effect of process variations becomes more pronounced which in turn effects the test time, test cost, and die yield. As devices become more unreliable, the probability of failure of a die increases, yield decreases affecting the quality of test and cost.Therefore, test time minimization and test cost reduction are important. Moreover, process variations can affect the performance of analog/mixed circuits. Therefore, the performance of a System On-Chip(SoC) which tends to integrate multiple band gap reference circuits (BGRs) is effected due to the wide variations caused in the behavior of the BGR as a result of increasing process variations. Calibration of the BGR is, thus, important in the test process so as to obtain accuracy in the measurement of the output voltage of BGR. Furthermore, as test time minimization and test cost reduction are important in a test process, Built-in Self Test (BIST) techniques have become more popular. To obtain accuracy in the measurement of the output voltage of BGR, a VCO-based zoom-in ADC architecture that was designed to calibrate the output of the BGR voltage which dictates the circuit performance. However, the zoom-voltages for the circuit are generated using a tester. As the number of such ADCs integrated on a SoC increase, the number of nodes to be accessed by the tester increase. Moreover, the capacitance of the probe affects the accuracy of the applied input voltages of the VCO-based ADC. Therefore, accessibility decreases with increase in scaling.Further, generating a wide range of inputs becomes burdensome for the tester. For all the above reasons, an on-chip DAC circuitry was proposed as a part of this thesis, to decrease the reliance on tester. The suggested DAC architecture is a simple resistor string whose resolution depends on the number of zoom-in voltages to be generated. This architecture has a linear and monotonic behavior which is very important as the VCO has a highly non-linear behavior. Thus, the voltages generated by the DAC should be accurate with minimum error so that the worst-case Integral Non-Linearity error (INL) is less than 1mV considering resistor mismatches over process variations. With the increase in the number of VCO-based ADCs on a chip, the test time savings increase exponentially. Thus, the introduction of an on-chip DAC circuitry offers various advantages like decreasing accessibility requirement during the test process, occupying less area, reducing test cost and most importantly, decreasing the reliance on tester.
ContributorsRavouri, Yestina (Author) / Ozev, Sule (Thesis advisor) / Ogras, Umit Y. (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2017
Description
Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power, better performance and lower hardware cost.
First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 and 3), x8 (Scheme 4) and x16 (Scheme 5) DRAM systems. All schemes have superior error correction performance due to the use of strong symbol-based codes. In addition, the use of erasure codes extends the lifetime of the 2D DRAM systems.
Next, two error correction schemes are presented for 3D DRAM memory systems. The first scheme is a rate-adaptive, two-tiered error correction scheme (RATT-ECC) that provides strong reliability (10^10x) reduction in raw FIT rate) for an HBM-like 3D DRAM system that services CPU applications. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing the reliability and timing performance.
The second scheme is a two-tiered error correction scheme (Config-ECC) that supports different sized accesses in GPU applications with strong reliability. It addresses the mismatch between data access size and fixed sized ECC scheme by designing a product code based flexible scheme. Config-ECC is built around a core unit designed for 32B access with a simple extension to support 64B and 128B accesses. Compared to fixed 32B and 64B ECC schemes, Config-ECC reduces the failure in time (FIT) rate by 200x and 20x, respectively. It also reduces the memory energy by 17% (in the dynamic mode) and 21% (in the static mode) compared to a state-of-the-art fixed 64B ECC scheme.
First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 and 3), x8 (Scheme 4) and x16 (Scheme 5) DRAM systems. All schemes have superior error correction performance due to the use of strong symbol-based codes. In addition, the use of erasure codes extends the lifetime of the 2D DRAM systems.
Next, two error correction schemes are presented for 3D DRAM memory systems. The first scheme is a rate-adaptive, two-tiered error correction scheme (RATT-ECC) that provides strong reliability (10^10x) reduction in raw FIT rate) for an HBM-like 3D DRAM system that services CPU applications. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing the reliability and timing performance.
The second scheme is a two-tiered error correction scheme (Config-ECC) that supports different sized accesses in GPU applications with strong reliability. It addresses the mismatch between data access size and fixed sized ECC scheme by designing a product code based flexible scheme. Config-ECC is built around a core unit designed for 32B access with a simple extension to support 64B and 128B accesses. Compared to fixed 32B and 64B ECC schemes, Config-ECC reduces the failure in time (FIT) rate by 200x and 20x, respectively. It also reduces the memory energy by 17% (in the dynamic mode) and 21% (in the static mode) compared to a state-of-the-art fixed 64B ECC scheme.
ContributorsChen, Hsing-Min (Author) / Chakrabarti, Chaitali (Thesis advisor) / Mudge, Trevor (Committee member) / Wu, Carole-Jean (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF.
ContributorsMatush, Bradley (Author) / Clark, Lawrence T (Thesis advisor) / Allee, David (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2010
Description
Within the near future, a vast demand for autonomous vehicular techniques can be forecast on both aviation and ground platforms, including autonomous driving, automatic landing, air traffic management. These techniques usually rely on the positioning system and the communication system independently, where it potentially causes spectrum congestion. Inspired by the spectrum sharing technique, Communications and High-Precision Positioning (CHP2) system is invented to provide a high precision position service (precision ~1cm) while performing the communication task simultaneously under the same spectrum. CHP2 system is implemented on the consumer-off-the-shelf (COTS) software-defined radio (SDR) platform with customized hardware. Taking the advantages of the SDR platform, the completed baseband processing chain, time-of-arrival estimation (ToA), time-of-flight estimation (ToF) are mathematically modeled and then implemented onto the system-on-chip (SoC) system. Due to the compact size and cost economy, the CHP2 system can be installed on different aerial or ground platforms enabling a high-mobile and reconfigurable network.
In this dissertation report, the implementation procedure of the CHP2 system is discussed in detail. It mainly focuses on the system construction on the Xilinx Ultrascale+ SoC platform. The CHP2 waveform design, ToA solution, and timing exchanging algorithms are also introduced. Finally, several in-lab tests and over-the-air demonstrations are conducted. The demonstration shows the best ranging performance achieves the ~1 cm standard deviation and 10Hz refreshing rate of estimation by using a 10MHz narrow-band signal over 915MHz (US ISM) or 783MHz (EU Licensed) carrier frequency.
In this dissertation report, the implementation procedure of the CHP2 system is discussed in detail. It mainly focuses on the system construction on the Xilinx Ultrascale+ SoC platform. The CHP2 waveform design, ToA solution, and timing exchanging algorithms are also introduced. Finally, several in-lab tests and over-the-air demonstrations are conducted. The demonstration shows the best ranging performance achieves the ~1 cm standard deviation and 10Hz refreshing rate of estimation by using a 10MHz narrow-band signal over 915MHz (US ISM) or 783MHz (EU Licensed) carrier frequency.
ContributorsYu, Hanguang (Author) / Bliss, Daniel (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Alkhateeb, Ahmed (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2020
Description
Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.
ContributorsOzel, Muhlis Kenan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
Description
Software-defined radio provides users with a low-cost and flexible platform for implementing and studying advanced communications and remote sensing applications. Two such applications include unmanned aerial system-to-ground communications channel and joint sensing and communication systems. In this work, these applications are studied.
In the first part, unmanned aerial system-to-ground communications channel models are derived from empirical data collected from software-defined radio transceivers in residential and mountainous desert environments using a small (< 20 kg) unmanned aerial system during low-altitude flight (< 130 m). The Kullback-Leibler divergence measure was employed to characterize model mismatch from the empirical data. Using this measure the derived models accurately describe the underlying data.
In the second part, an experimental joint sensing and communications system is implemented using a network of software-defined radio transceivers. A novel co-design receiver architecture is presented and demonstrated within a three-node joint multiple access system topology consisting of an independent radar and communications transmitter along with a joint radar and communications receiver. The receiver tracks an emulated target moving along a predefined path and simultaneously decodes a communications message. Experimental system performance bounds are characterized jointly using the communications channel capacity and novel estimation information rate.
In the first part, unmanned aerial system-to-ground communications channel models are derived from empirical data collected from software-defined radio transceivers in residential and mountainous desert environments using a small (< 20 kg) unmanned aerial system during low-altitude flight (< 130 m). The Kullback-Leibler divergence measure was employed to characterize model mismatch from the empirical data. Using this measure the derived models accurately describe the underlying data.
In the second part, an experimental joint sensing and communications system is implemented using a network of software-defined radio transceivers. A novel co-design receiver architecture is presented and demonstrated within a three-node joint multiple access system topology consisting of an independent radar and communications transmitter along with a joint radar and communications receiver. The receiver tracks an emulated target moving along a predefined path and simultaneously decodes a communications message. Experimental system performance bounds are characterized jointly using the communications channel capacity and novel estimation information rate.
ContributorsGutierrez, Richard (Author) / Bliss, Daniel W (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Ogras, Umit Y. (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Arizona State University (Publisher)
Created2018
Description
Microelectronic circuits are prone to upsets in the natural and manmade radiation environments. As the scaling of these circuits continues, they have become more susceptible to these upsets. In highly scaled technologies even the terrestrial radiation environment is becoming increasing source of soft errors in integrated circuits. Simultaneously the means of protecting circuits via the process technology have become more and more limited. As a result, design techniques to mitigate the upsets are becoming a requirement in an ever-growing list of applications. This work begins with an overview of radiation effects in integrated circuits. The phenomenology of upsets is discussed along with their basic mechanisms. How these effects are quantified in microelectronic circuits is then presented along with a summary of simulation methods. This is followed with a survey of the state of the field for radiation hardening by design techniques and a selection of radiation hardened flip flop designs.
Upsets within these sequential circuits like flip flops can lead to process failure or erroneous execution and thus much of the radiation hardening effort is focused on protecting them. This work applies a systematic approach to radiation hardening by design to a temporally hardened flip flop and implements it in a 14nm finFET process.
Forty-nine delay circuits are analyzed and compared on multiple performance metrics before a down select for integration. The resultant flip flop circuit is shown to have a minimum critical charge 3x higher than the baseline library flip flop. Physical design of the flip flop is outlined and nine configurations consisting of three delay lengths and three levels if bit interleaving are accomplished. The circuits are integrated as shift registers in a radiation test chip and exposed to heavy ion testing.
Results of heavy ion testing demonstrate a threshold LET increase of approximately 6 MeV∙cm2/mg with marginal increases in saturation cross section for the target LET range. A failure mode is detected while storing ones, that has both area and time dependence. Substrate charge collection is suggested as a cause and a new circuit design is presented to mitigate the error with minimal performance impact.
ContributorsYoungSciortino, Clifford Samuel (Author) / Clark, Lawrence T (Thesis advisor) / Guertin, Steven M (Committee member) / Marinella, Matthew J (Committee member) / Arizona State University (Publisher)
Created2022
Description
Deep neural networks (DNNs), as a main-stream algorithm for various AI tasks, achieve higher accuracy at the cost of increased computational complexity and model size, posing great challenges to hardware platforms. This dissertation first tackles the design challenges of resistive random-access-memory (RRAM) based in-memory computing (IMC) architectures. A new metric, model stability from the loss landscape, is proposed to help shed light on accuracy under variations and model compression and guide a novel variation-aware training (VAT) solution. The proposed method effectively improves post-mapping accuracy of multiple datasets. Next, a hybrid RRAM/SRAM IMC DNN inference accelerator is developed, that integrates an RRAM-based IMC macro, a reconfigurable SRAM-based multiply-accumulate (MAC) macro, and a programmable shifter. The hybrid IMC accelerator fully recovers the inference accuracy post the mapping. Furthermore, this dissertation researches on architectural optimizations for high IMC utilization, low on-chip communication cost, and low energy-delay product (EDP), including on-chip interconnect design, PE array utilization, and tile-to-router mapping and scheduling. The optimal choice of on-chip interconnect results in up to 6x improvement in energy-delay-area product for RRAM IMC architectures. Furthermore, the PE and NoC optimizations show up to 62% improvement in PE utilization, 78% reduction in area, and 78% lower energy-area product for a wide range of modern DNNs. Finally, this dissertation proposes a novel chiplet-based IMC benchmarking simulator, SIAM, and a heterogeneous chiplet IMC architecture to address the limitations of a monolithic DNN accelerator. SIAM utilizes model-based and cycle-accurate simulation to provide a scalable and flexible architecture. SIAM is calibrated against a published silicon result, SIMBA, from Nvidia. The heterogeneous architecture utilizes a custom mapping with a bank of big and little chiplets, and a hybrid network-on-package (NoP) to optimize the utilization, interconnect bandwidth, and energy efficiency. The proposed big-little chiplet-based RRAM IMC architecture significantly improves energy efficiency at lower area, compared to conventional GPUs. In summary, this dissertation comprehensively investigates novel methods that encompass device, circuits, architecture, packaging, and algorithm to design scalable high-performance and energy-efficient IMC architectures.
ContributorsKrishnan, Gokul (Author) / Cao, Yu (Thesis advisor) / Seo, Jae-Sun (Committee member) / Chakrabarti, Chaitali (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2022