Matching Items (182)
Description
Eurocentrism in early 20th-century music history in Latin America demonstrates political and racial preferences that placed foreign art music over local music making practices. After the Mexican Revolution (roughly 1910–20), Mexican political and cultural leaders pushed for a “universal” aesthetic in their nation’s art music, implicitly devaluing musical references to Indigenous cultures. This contradicts the era’s indigenist cultural revolution popularized as an “Aztec Renaissance” that celebrated Mexico’s renewed notion of mestizaje (European-Indigenous racial mixture) in music and art. The Mexican elite turned to foreign intellectuals such as Adolfo Salazar (1890–1958), the Spanish-born composer and music critic who came to Mexico as an exile in 1939, to link Mexico’s postcolonial culture with the intellectual inheritance of Europe.This thesis offers discursive analysis of Salazar’s writings in the context of his Mexican years, revealing subtexts of Spanish racial and cultural superiority that indirectly served the elitist agendas of Mexican diplomats and musical tastemakers such as Carlos Chávez (1899–1978). Salazar’s hegemonic legacy in Spanish-language musicology has often been left unquestioned and therefore I assess his influence alongside the development of a music-historical paradigm that defined 20th-century Mexican art music as an international phenomenon. I argue that Salazar’s Spanish-oriented music history established dominance over musicmaking practices in Mexico through demeaning allusions to mestizaje and social hierarchies within musical nationalism. By considering Salazar’s role in Mexican musical nationalism, my thesis reveals how Eurocentric music history writing coincided with colonialist Mexican politics, legitimizing foreign intellectualism over local cultural processes.
ContributorsHeyen, Adam David (Author) / Feisst, Sabine (Thesis advisor) / Bolanos, Gabriel (Committee member) / Saikia, Yasmin (Committee member) / Arizona State University (Publisher)
Created2022
Description
Adversarial threats of deep learning are increasingly becoming a concern due to the ubiquitous deployment of deep neural networks(DNNs) in many security-sensitive domains. Among the existing threats, adversarial weight perturbation is an emerging class of threats that attempts to perturb the weight parameters of DNNs to breach security and privacy.In this thesis, the first weight perturbation attack introduced is called Bit-Flip Attack (BFA), which can maliciously flip a small number of bits within a computer’s main memory system storing the DNN weight parameter to achieve malicious objectives. Our developed algorithm can achieve three specific attack objectives: I) Un-targeted accuracy degradation attack, ii) Targeted attack, & iii) Trojan attack. Moreover, BFA utilizes the rowhammer technique to demonstrate the bit-flip attack in an actual computer prototype. While the bit-flip attack is conducted in a white-box setting, the subsequent contribution of this thesis is to develop another novel weight perturbation attack in a black-box setting. Consequently, this thesis discusses a new study of DNN model vulnerabilities in a multi-tenant Field Programmable Gate Array (FPGA) cloud under a strict black-box framework. This newly developed attack framework injects faults in the malicious tenant by duplicating specific DNN weight packages during data transmission between off-chip memory and on-chip buffer of a victim FPGA. The proposed attack is also experimentally validated in a multi-tenant cloud FPGA prototype. In the final part, the focus shifts toward deep learning model privacy, popularly known as model extraction, that can steal partial DNN weight parameters remotely with the aid of a memory side-channel attack. In addition, a novel training algorithm is designed to utilize the partially leaked DNN weight bit information, making the model extraction attack more effective. The algorithm effectively leverages the partial leaked bit information and generates a substitute prototype of the victim model with almost identical performance to the victim.
ContributorsRakin, Adnan Siraj (Author) / Fan, Deliang (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Seo, Jae-Sun (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2022
Description
Artificial Intelligence (AI) and Machine Learning (ML) techniques have come a long way since their inception and have been used to build intelligent systems for a wide range of applications in everyday life. However they are very computationintensive and require transfer of large volume of data from memory to the computation units. This memory access time constitute significant part of the computational latency and a performance bottleneck. To address this limitation and the ever-growing demand for implementation in hand-held and edge-devices, In-memory computing (IMC) based AI/ML hardware accelerators have emerged. First, the dissertation presents an IMC static random access memory (SRAM) based hardware modeling and optimization framework. A unified systematic study closely models the IMC hardware, and investigates how a number of design variables and non-idealities (e.g. device mismatch and ADC quantization) affect the Deep Neural Network (DNN) accuracy of the IMC design. The framework allows co-optimized selection of different design variables accounting for sources of noise in IMC hardware and robust implementation of a high accuracy DNN. Next, it presents a kNN hardware accelerator in 65nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The accelerator combines an IMC SRAM that is developed for binarized deep neural networks and other digital hardware that performs top-k sorting. The simulated k Nearest Neighbor accelerator design processes up to 17.9 million query vectors per second while consuming 11.8 mW, demonstrating >4.8× energy-efficiency improvement over prior works. This dissertation also presents a novel floating-point precision IMC (FP-IMC) macro with a hybrid architecture that configurably supports two Floating Point (FP) precisions. Implementing FP precision MAC has been a challenge owing to its complexity. The design is implemented on 28nm CMOS, and taped-out on chip demonstrating 12.1 TFLOPS/W and 66.1 TFLOPS/W for 8-bit Floating Point (FP8) and Block Floating point (BF8) respectively. Finally, another iteration of the FP design is presented that is modeled to support multiple precision modes from FP8 up to FP32. Two approaches to the architectural design were compared illustrating the throughput-area overhead trade-off. The simulated design shows a 2.1 × normalized energy-efficiency compared to the on-chip implementation of the FP-IMC.
ContributorsSaikia, Jyotishman (Author) / Seo, Jae-Sun (Thesis advisor) / Chakrabarti, Chaitali (Thesis advisor) / Fan, Deliang (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2023
Description
While much has been written on the history of Education Concerts in the United States, there is a void in research focused on actual content, structure, and purposes of these concerts. This document seeks to fill this void through a detailed examination of salient aspects of Education Concerts, including programming, structure, rehearsal, and performance considerations. In conjunction with my research, I will draw on my first-hand experience as Associate Conductor of the Seattle Symphony, providing a glimpse into the creative challenges and solutions that confront a contemporary orchestra. Additionally, my research endeavors to discover ways of transforming the historically rigid model of orchestral operations into a structure that embraces diversity, equity, and inclusion, encourages connections, and sparks curiosity. The goal of this research, therefore, is to provide tangible references and practical guidance to the conductor or administrator who is venturing into the richness of Education Concert programming and performance in today’s everchanging orchestral landscape.
ContributorsXia, Sunny Xuecong (Author) / Caslor, Jason (Thesis advisor) / Bolanos, Gabriel (Committee member) / Feisst, Sabine (Committee member) / Meyer, Jeffery (Committee member) / Arizona State University (Publisher)
Created2023
Description
In recent years, Artificial Intelligence (AI) (e.g., Deep Neural Networks (DNNs), Transformer) has shown great success in real-world applications due to its superior performance in various cognitive tasks. The impressive performance achieved by AI models normally accompanies the cost of enormous model size and high computational complexity, which significantly hampers their implementation on resource-limited Cyber-Physical Systems (CPS), Internet-of-Things (IoT), or Edge systems due to their tightly constrained energy, computing, size, and memory budget. Thus, the urgent demand for enhancing the \textbf{Efficiency} of DNN has drawn significant research interests across various communities.
Motivated by the aforementioned concerns, this doctoral research has been mainly focusing on Enabling Deep Learning at Edge: From Efficient and Dynamic Inference to On-Device Learning. Specifically, from the inference perspective, this dissertation begins by investigating a hardware-friendly model compression method that effectively reduces the size of AI model while simultaneously achieving improved speed on edge devices. Additionally, due to the fact that diverse resource constraints of different edge devices, this dissertation further explores dynamic inference, which allows for real-time tuning of inference model size, computation, and latency to accommodate the limitations of each edge device. Regarding efficient on-device learning, this dissertation starts by analyzing memory usage during transfer learning training. Based on this analysis, a novel framework called "Reprogramming Network'' (Rep-Net) is introduced that offers a fresh perspective on the on-device transfer learning problem. The Rep-Net enables on-device transferlearning by directly learning to reprogram the intermediate features of a pre-trained model. Lastly, this dissertation studies an efficient continual learning algorithm that facilitates learning multiple tasks without the risk of forgetting previously acquired knowledge. In practice, through the exploration of task correlation, an interesting phenomenon is observed that the intermediate features are highly correlated between tasks with the self-supervised pre-trained model. Building upon this observation, a novel approach called progressive task-correlated layer freezing is proposed to gradually freeze a subset of layers with the highest correlation ratios for each task leading to training efficiency.
ContributorsYang, Li (Author) / Fan, Deliang (Thesis advisor) / Seo, Jae-Sun (Committee member) / Zhang, Junshan (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2023
Description
Modern-day automobiles are becoming more connected and reliant on wireless connectivity. Thus, automotive electronics can be both a cause of and highly sensitive to electromagnetic interference (EMI), and the consequences of failure can be fatal. Technology advancements in engineering have brought several features into the automotive field but at the expense of electromagnetic compatibility issues. Automotive EMC problems are the result of the emissions from electronic assemblies inside a vehicle and the susceptibility of the electronics when exposed to external EMI sources. In both cases, automotive EMC problems can cause unintended changes in the automotive system operation. Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state-of-the-art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this dissertation an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via the substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle, and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.
ContributorsRay, Abhishek (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2023
Description
Deep neural networks (DNNs), as a main-stream algorithm for various AI tasks, achieve higher accuracy at the cost of increased computational complexity and model size, posing great challenges to hardware platforms. This dissertation first tackles the design challenges of resistive random-access-memory (RRAM) based in-memory computing (IMC) architectures. A new metric, model stability from the loss landscape, is proposed to help shed light on accuracy under variations and model compression and guide a novel variation-aware training (VAT) solution. The proposed method effectively improves post-mapping accuracy of multiple datasets. Next, a hybrid RRAM/SRAM IMC DNN inference accelerator is developed, that integrates an RRAM-based IMC macro, a reconfigurable SRAM-based multiply-accumulate (MAC) macro, and a programmable shifter. The hybrid IMC accelerator fully recovers the inference accuracy post the mapping. Furthermore, this dissertation researches on architectural optimizations for high IMC utilization, low on-chip communication cost, and low energy-delay product (EDP), including on-chip interconnect design, PE array utilization, and tile-to-router mapping and scheduling. The optimal choice of on-chip interconnect results in up to 6x improvement in energy-delay-area product for RRAM IMC architectures. Furthermore, the PE and NoC optimizations show up to 62% improvement in PE utilization, 78% reduction in area, and 78% lower energy-area product for a wide range of modern DNNs. Finally, this dissertation proposes a novel chiplet-based IMC benchmarking simulator, SIAM, and a heterogeneous chiplet IMC architecture to address the limitations of a monolithic DNN accelerator. SIAM utilizes model-based and cycle-accurate simulation to provide a scalable and flexible architecture. SIAM is calibrated against a published silicon result, SIMBA, from Nvidia. The heterogeneous architecture utilizes a custom mapping with a bank of big and little chiplets, and a hybrid network-on-package (NoP) to optimize the utilization, interconnect bandwidth, and energy efficiency. The proposed big-little chiplet-based RRAM IMC architecture significantly improves energy efficiency at lower area, compared to conventional GPUs. In summary, this dissertation comprehensively investigates novel methods that encompass device, circuits, architecture, packaging, and algorithm to design scalable high-performance and energy-efficient IMC architectures.
ContributorsKrishnan, Gokul (Author) / Cao, Yu (Thesis advisor) / Seo, Jae-Sun (Committee member) / Chakrabarti, Chaitali (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2022
Description
High-temperature mechanical behaviors of metal alloys and underlying microstructural variations responsible for such behaviors are essential areas of interest for many industries, particularly for applications such as jet engines. Anisotropic grain structures, change of preferred grain orientation, and other transformations of grains occur both during metal powder bed fusion additive manufacturing processes, due to variation of thermal gradient and cooling rates, and afterward during different thermomechanical loads, which parts experience in their specific applications, could also impact its mechanical properties both at room and high temperatures. In this study, an in-depth analysis of how different microstructural features, such as crystallographic texture, grain size, grain boundary misorientation angles, and inherent defects, as byproducts of electron beam powder bed fusion (EB-PBF) AM process, impact its anisotropic mechanical behaviors and softening behaviors due to interacting mechanisms. Mechanical testing is conducted for EB-PBF Ti6Al4V parts made at different build orientations up to 600°C temperature. Microstructural analysis using electron backscattered diffraction (EBSD) is conducted on samples before and after mechanical testing to understand the interacting impact that temperature and mechanical load have on the activation of certain mechanisms. The vertical samples showed larger grain sizes, with an average of 6.6 µm, a lower average misorientation angle, and subsequently lower strength values than the other two horizontal samples. Among the three strong preferred grain orientations of the α phases, <1 1 2 ̅ 1> and <1 1 2 ̅ 0> were dominant in horizontally built samples, whereas the <0 0 0 1> was dominant in vertically built samples. Thus, strong microstructural variation, as observed among different EB-PBF Ti6Al4V samples, mainly resulted in anisotropic behaviors. Furthermore, alpha grain showed a significant increase in average grain size for all samples with the increasing test temperature, especially from 400°C to 600°C, indicating grain growth and coarsening as potential softening mechanisms along with temperature-induced possible dislocation motion. The severity of internal and external defects on fatigue strength has been evaluated non-destructively using quantitative methods, i.e., Murakami’s square root of area parameter model and Basquin’s model, and the external surface defects were rendered to be more critical as potential crack initiation sites.
ContributorsMian, Md Jamal (Author) / Ladani, Leila (Thesis advisor) / Razmi, Jafar (Committee member) / Shuaib, Abdelrahman (Committee member) / Mobasher, Barzin (Committee member) / Nian, Qiong (Committee member) / Arizona State University (Publisher)
Created2022
Description
Following mixed method ethnographic research conducted between January 2020 and January 2022, this thesis discusses how United States all-female mariachi musicians, or mariacheras, express femininity in the mariachi femenil. Mariachis femeniles are all-female mariachis. Building upon Mary Lee Mulholland’s (2013) discussion of how mariacheras in Jalisco are often valued more for their physical appearance than for their musical skills, this thesis investigates how similar phenomena manifest in the United States’ professional mariachi femenil circuit. Applying a Chicana Feminisms lens to a collection of 28 mariachera plática-interviews, generational and transborder mariachi knowledge production, visual expressions of mariachi femininity, and aural feminine expressions in the mariachi setting are complicated. Each participant details what it means to be a mariachera, breaking down concepts of purity in the face of dichotomous cultural gender expectation and the genre’s visual expectations of how female musicians should present themselves in society. These sociocultural phenomena led these women in many ways to disidentify and resignify various pieces of the mariachi tradition to “carve out” their own space in the practice, expressing the concern they want to be respected as a musician, not as just a visual object. Ultimately, the “carved out” space allows mariacheras to perform a “different” sound of mariachi—a negotiation of strength, femininity, and balancing sociocultural expectations of the mariachera in and out of performance.
ContributorsFlores, Cameo Rachelle (Author) / Fossum, Dave (Thesis advisor) / Estrada, Emir (Committee member) / Feisst, Sabine (Committee member) / Wells, Christi Jay (Committee member) / Arizona State University (Publisher)
Created2022
Description
Computer vision is becoming an essential component of embedded system applications such as smartphones, wearables, autonomous systems and internet-of-things (IoT). These applications are generally deployed into environments with limited energy, memory bandwidth and computational resources. This trend is driving the development of energy-effi cient image processing solutions from sensing to computation. In this thesis, diff erent alternatives are explored to implement energy-efficient computer vision systems. First, I present a fi eld programmable gate array (FPGA) implementation of an adaptive subsampling algorithm for region-of-interest (ROI) -based object tracking. By implementing the computationally intensive sections of this algorithm on an FPGA, I aim to offl oad computing resources from energy-ineffi cient graphics processing units (GPUs) and/or general-purpose central processing units (CPUs). I also present a working system executing this algorithm in near real-time latency implemented on a standalone embedded device. Secondly, I present a neural network-based pipeline to improve the performance of event-based cameras in non-ideal optical conditions. Event-based cameras or dynamic vision sensors (DVS) are bio-inspired sensors that measure logarithmic per-pixel brightness changes in a scene. Their advantages include high dynamic range, low latency and ultra-low power when compared to standard frame-based cameras. Several tasks have been proposed to take advantage of these novel sensors but they rely on perfectly calibrated optical lenses that are in-focus. In this work I propose a methodto reconstruct events captured with an out-of-focus event-camera so they can be fed into an intensity reconstruction task. The network is trained with a dataset generated by simulating defocus blur in sequences from object tracking datasets such as LaSOT and OTB100. I also test the generalization performance of this network in scenes captured with a DAVIS event-based sensor equipped with an out-of-focus lens.
ContributorsTorres Muro, Victor Isaac (Author) / Jayasuriya, Suren (Thesis advisor) / Spanias, Andreas (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2022